A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET

📋 论文概要

该论文提出了一款面向物联网设备的25mm² SoC，通过贝叶斯语音去噪和基于注意力的序列到序列学习，实现了18ms的噪声鲁棒语音到文本延迟。解决了之前ASR芯片在噪声和多说话人场景下性能差的问题。

💡 主要创新点

• 采用贝叶斯方法进行语音去噪，提升噪声环境下的识别鲁棒性
• 集成基于注意力的序列到序列模型，实现端到端语音到文本转换，延迟仅18ms
• SoC面积仅为25mm²，适合物联网设备功耗和面积限制

🏷 关键词

📄 原文摘要

Marco Donato2, Paul N. Whatmough1,3, Alexander M. Rush4, David Brooks1, Gu-Yeon Wei1 Harvard University, Cambridge, MA Tufts University, Medford, MA 3 ARM, Boston, MA 4 Cornell University, New York, NY 1 2 Automatic speech recognition (ASR) using deep learning is essential for user interfaces on IoT devices. However, previously published ASR chips [4-7] do not consider realistic operating conditions, which are typically noisy and may include more than one speaker. Furthermore, several of these works have implemented only small-vocabulary tasks, such as keyword-spotting (KWS), where context-blind deep neural network (DNN) algorithms are adequate. However, for large-vocabulary tasks (e.g., >100k words), the more complex bidirectional RNNs with an attention mechanism [1] provide context learning in long sequences, which improve ASR accuracy by up to 62% on the 200kwords LibriSpeech dataset, compared to a simpler unidirectional RNN (Fig. 9.8.1).

👥 作者与机构

Thierry Tambe1, En-Yu Yang1, Glenn G. Ko1, Yuji Chai1, Coleman Hooper1,