A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-onChip with I/Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum Dots

📋 论文概要

该论文提出了一款全集成40nm低温CMOS（Cryo-CMOS）片上系统，包含I/Q接收机和频率合成器，用于可扩展的量子计算应用。芯片通过片上PLL和VCO产生本振信号，支持5-6.5GHz频率范围，实现了低温环境下的高性能信号处理。

💡 主要创新点

• 首次在40nm CMOS工艺上实现了全集成Cryo-CMOS SoC，集成I/Q接收机和频率合成器，适用于量子计算系统。
• 采用12.8GHz LC VCO搭配可编程分频器，实现宽调谐范围（10.5-16.5GHz），通过二分频产生6.4GHz正交本振信号，支持5.25-8.25GHz调谐。

🏷 关键词

📄 原文摘要

Quantum Motion Technologies, Leeds, United Kingdom differential-to-single-ended buffer for 50Ω output match. The LO signal for downconversion is generated on chip by an analog charge-pump integer-N PLL with a programmable divider to ensure locking range to the reference clock, built around a 12.8GHz LC voltage-controlled oscillator (VCO) followed by a current-mode logic (CML) divider by 2, to generate a 6.4GHz quadrature signal. The VCO is tunable between 10.5GHz and 16.5GHz, thus resulting in a LO signal that can be tuned between 5.25GHz and 8.25GHz. A serial-to-parallel interface (SPI) is used for digital control and tunability during testing. 1 2 *Equally-Credited Authors (ECAs) Quantum computing holds the promise to solve many of today’s intractable problems.

👥 作者与机构

Andrea Ruffino*1, Yatao Peng*1, Tsung-Yeh Yang2, John Michniewicz3,

Miguel Fernando Gonzalez-Zalba2,4, Edoardo Charbon1 EPFL, Neuchâtel, Switzerland Hitachi, Cambridge, United Kingdom 3 University of Cambridge, Cambridge, United Kingdom