A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture

📋 论文概要

该论文提出了一款176层堆叠的512Gb 3b/cell 3D-NAND闪存，采用外围电路置于存储阵列下方（PUC）架构，实现了10.8Gb/mm2的高存储密度，解决了数据增长对更高密度存储的需求。

💡 主要创新点

• 首次实现176层堆叠的3D-NAND闪存，显著提升存储容量和密度。
• 采用3b/cell（每单元3比特）存储技术，在保持可靠性的同时提高单位面积存储密度。
• 创新性地使用外围电路置于存储阵列下方（PUC）架构，有效减小芯片面积，进一步提升密度。

🏷 关键词

📄 原文摘要

Hyunsoo Lee, Sungmook Lim, Sun-Young Jung, Hyeongjin Choi, Taikyu Kang, Gwan Park, Chul-Woo Yang, Jeong-Gil Choi, Gwihan Ko, Jaehyeon Shin, Ingon Yang, Junghoon Nam, Hyeokchan Sohn, Seok-In Hong, Yohan Jeong, Sung-Wook Choi, Changwoon Choi, Hyun-Soo Shin, Junyoun Lim, Dongkyu Youn, Sanghyuk Nam, Juyeab Lee, Myungkyu Ahn, Hoseok Lee, Seungpil Lee, Jongmin Park, Kichang Gwon, Woopyo Jeong, Jungdal Choi, Jinkook Kim, Kyo-Won Jin SK hynix Semiconductor, Icheon, Korea With an explosive growth of data generated by various applications, one of the most important topics of the current era is to increase the storage capacity. The evolution from 2D planar NAND to 3D NAND enables the development of high-density storage by increasing the number of stacked word-lines (WLs) in a smaller footprint. The industry has moved beyond 96-stacked-WL and achieved a 128-stacked 3D NAND. A 128-stacked 3b/cell 3D NAND with a density of 7.8Gb/mm2 was reported recently, based on a

👥 作者与机构

Jae-Woo Park, Doogon Kim, Sunghwa Ok, Jaebeom Park, Taeheui Kwon,