A 365fsrms-Jitter and −63dBc-Fractional Spur 5.3GHz-RingDCO-Based Fractional-N DPLL Using a DTC Second/ThirdOrder Nonlinearity Cancelation and a Probability-DensityShaping ΔΣM

📋 论文概要

本文提出了一种基于环形DCO的分数-N数字PLL，利用数字时间转换器（DTC）的二阶/三阶非线性补偿技术，有效抑制了由DTC非线性引起的分数杂散，实现了365fsrms的低抖动和-63dBc的分数杂散性能，适用于5G通信中的高频调制需求。

💡 主要创新点

• 提出了一种针对DTC二阶和三阶非线性的补偿技术，大幅降低分数杂散。
• 采用环形DCO实现了5.3GHz的低抖动输出，满足256-QAM等高阶调制要求。

🏷 关键词

📄 原文摘要

data-rates by combining more carrier components, 5G RF transceivers require many carrier frequencies, resulting in the situation of many LC PLLs occupying a large silicon area. Ring-oscillator-based digital PLLs (RO-DPLLs) with a fractional resolution obviously can be a good solution, but conventional ΔΣM-based PLLs hardly achieve a low enough jitter to satisfy the requirements of high-order modulations, such as 256-QAM. Currently, the use of a digital-to-time converter (DTC) to cancel the quantization noise (Q-noise) is popular, but fractional spurs due to the nonlinearity of the DTC (NLDTC) are a critical problem, especially for RO-DPLLs that require a wide bandwidth to suppress the RO jitter. The piecewise linearization of the DTC code can

👥 作者与机构

Hangi Park*1, Chanwoong Hwang*1, Taeho Seong*1,2, Yongsun Lee3, Jaehyouk Choi1

KAIST, Daejeon, Korea Ulsan National Institute of Science and Technology, Ulsan, Korea 3 Samsung Electronics, Hwaseong, Korea 1 2 *Equally Credited Authors (ECAs) To maximize