A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET peaking inductor is leveraged to resonate out the parasitic & transistor gate capacitances. A flipped voltage follower buffer is used to isolate the CTLE from the 16 TAHs. The DCgain normalized frequency response at the output of the AFE for various CTLE settings is shown in the Fig. 8.7.3.

📋 论文概要

该论文提出了一款基于ADC-DSP的112Gb/s PAM-4收发器，适用于信道损耗超过40dB的长距离应用。采用7nm FinFET工艺，通过4抽头FIR和7抽头预失真DSP引擎以及低功耗串行器设计，实现了高数据速率下的均衡和低功耗。

💡 主要创新点

• 采用全数字ADC-DSP架构实现112Gb/s PAM-4信号处理，支持>40dB信道损耗的长距离传输。
• 集成4-tap FIR和7-tap预失真的DSP引擎，通过灵活的数字均衡提升链路性能。
• 多级分区的64:2串行器设计，在高速率下优化功耗与面积。

🏷 关键词

📄 原文摘要

K. Raviprakash1, L. Tse1, M. Davoodi4, M. Takefman3, N. Fan4, P. Prabha4, Q. Liu2, Q. Wang1, R. Nagulapalli5, S. Cyrusian4, S. Jantzi4, S. Scouten3, T. Dusatko6, T. Setya3, V. Giridharan1, V. Gurumoorthy1, V. Karam3, W. Liew2, Y. Liao1, Y. Ou1 Figure 8.7.4 shows the block diagram of the half-rate transmitter. With 4-tap FIR and 7-tap predistortion embedded, the DSP engine generates the pre-emphasized 64 parallelstreams of data into the 64:2 serializer, which is partitioned into multiple stages in order to achieve minimum power. Duty-cycle correction circuitry corrects the differential halfrate clocks driving the 2:1 serializer. A sub-UI bit-equalization technique is used inside the pre-driver and in the clock paths to minimize ISI and jitter-amplification. Within a chain of four inverters, the output of the final inverter is fed back to the output of the first inverter via a CMOS transmission gate. After the pre-driver, the output driver is a

👥 作者与机构

P. Mishra1, A. Tan1, B. Helal1, C.R. Ho1, C. Loi1, J. Riani1, J. Sun2, K. Mistry3,