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本文介绍了一款用于5G移动SoC的新型CPU子系统，其中高性能核心实现了3GHz时钟频率。该设计旨在满足5G应用对处理能力的高要求，并集成了三齿轮架构以优化能效。
Gokulakrishnan Manoharan1, Ericbill Wang2, Gordon Gammie1, Efron Ho1, Anand Rajagopalan1, Lee-Kee Yong1, Ramu Madhavaram1, Madhur Jagota1, Chi-Jui Chung1, Sudhakar Maruthi1, Jenny Wiedemeier1, Tao Chen1, Henry Hsieh2, Daniel Dia2, Amjad Sikiligiri1, Manzur Rahman1, Barry Chen2, Curtis Lin2, Vincent Lin2, Elly Chiang2, Cheng-Yuh Wu2, Po-Yang Hsu2, Jason Tsai2, Wade Wu2, Achuta Thippana1, SA Huang2 MediaTek, Austin, TX MediaTek, Hsinchu, Taiwan 1 2 This paper describes a new CPU subsystem featured in a 5G mobile SoC. The HighPerformance (HP) core achieves a 3GHz clock frequency with full production yield across the fabrication range and operating environment. In contrast to previously published work [1], a third, balanced-performance (BP), gear is introduced which features a poweroptimized implementation of the high-performance (HP) core. Physical implementation differences of the BP and HP cores are illustrated, while circuit techniques developed to
Hsinchen Chen1, Rolf Lagerquist1, Ashish Nayak1, Hugh Mair1,