A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

📋 论文概要

本文提出一款22nm工艺的4Mb 8bit精度ReRAM存内计算宏，通过优化的读写操作和电流镜技术，实现了11.91至195.7 TOPS/W的能效，适用于微型AI边缘设备，解决了传统架构中数据搬运的功耗和延迟问题。

💡 主要创新点

• 采用脉冲调制和电流镜实现多精度计算，优化了WLP1/WLP2读写相位流程
• 通过上下电流镜和开关控制，在不增加功耗的前提下提升计算精度和能效

📄 原文摘要

Sheng-Po Huang1, Fu-Chun Chang1, Peng Chen1, Ta-Wei Liu1, Chuan-Jia Jhang1, Chin-I Su2, Win-San Khwa2, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Yu-Der Chih2, Tsung-Yung Jonathan Chang2, Meng-Fan Chang1,2 National Tsing Hua University, Hsinchu, Taiwan TSMC, Hsinchu, Taiwan 1 to reset C0 and CC to 0V. In the WLP1 phase, the generation of voltage at node SUM (VSUM-P1) is similar to that of WLP2 phase, but with up to 7 SW0/EN1 pulses to sample IWDL0 and no readout operation at the end. In the WLP0 phase, SW1 is off, while SW3 is on to downscale IDL through current-mirror pairs P1-P3 with a 1/16 scaling ratio, resulting IWDL1 = 1/16·IDL. Here, EN2=1 and SW2 is turned on up to 7 times to sample IWDL1 and charge the node STACK connected to capacitors CC and CS, which make node STACK has matching capacitance at node SUM. Then, IWDL1 charges capacitor CS to generate stacking voltage (VSTACK, maximum value is 1/9·VDD) at node STACK. The value

👥 作者与机构

Cheng-Xin Xue*1, Je-Min Hung*1, Hui-Yao Kao1, Yen-Hsiang Huang1,