A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT/C-Cancelling S&H and Delta-Sigma ADC

📋 论文概要

本文提出一种高速背照式堆叠CMOS图像传感器，采用列并行kT/C噪声消除采样保持和Delta-Sigma ADC，解决了高分辨率大画幅图像传感器中速度和噪声的挑战。适用于数字相机、安防和工业自动化等应用。

💡 主要创新点

• 采用背照式堆叠结构，提高感光效率和集成度。
• 列并行kT/C噪声消除采样保持电路，有效降低复位噪声。
• 列并行Delta-Sigma ADC，实现高速高精度模数转换。

🏷 关键词

📄 原文摘要

Takashi Moue1, Daisuke Yamazaki1, Kazutoshi Kodama1, Masafumi Okano1, Takafumi Morikawa1, Kazuyoshi Yamashita1, Osamu Oka2, Itai Shvartz3, Golan Zeituni3, Ariel Benshem3, Noam Eshel3, Yoshiaki Inada1 Sony Semiconductor Solutions, Kanagawa, Japan Sony Semiconductor Manufacturing, Kumamoto, Japan 3 Sony Electronics, Ra’anana, Israel 1 2 In recent years, there has been growing demand for high-resolution and large-format CMOS image sensors in Digital Still Camera, Security, and Factory Automation uses. In addition, new uses such as airborne mapping [1] are now being reported. Focusing on the camera market, there is currently demand for simultaneously realizing high image quality, high frame rate, and low power consumption, all within a larger-than-APS-C format. For most cases, the single-slope ADC (SS ADC) [2] architecture is used in commercialized CMOS image sensors. In order to accelerate frame rate, the countingclock frequency can be increased up to 2.376GHz as demonstrated in [3], but

👥 作者与机构

Chihiro Okada1, Koushi Uemura1, Luong Hung1, Kouji Matsuura1,