A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Computein-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification

📋 论文概要

本文提出了一款基于40nm工艺的64Kb RRAM计算存储宏，通过主动反馈读取和数字辅助技术实现了读干扰容忍，解决了RRAM在AI和图分析等内存密集型工作负载中的可靠性和能效问题。该宏支持可编程计算精度（1-9位），并达到了56.67TOPS/W的高能效。

💡 主要创新点

• 提出主动反馈读取（Active-Feedback-Based Read）电路，有效抑制读干扰，提高RRAM读取可靠性。
• 集成计算存储（Compute-in-Memory）与数字处理，支持可编程精度，兼顾灵活性与能效。
• 在40nm工艺下实现64Kb容量，能效达56.67TOPS/W，优于传统SRAM方案。

🏷 关键词

📄 原文摘要

memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) higher bit-density (2-4× of SRAM), (2) CMOS process/voltage compatibility, (3) nano-second read (RD) and (4) non-volatility has emerged as a promising candidate [1]. In spite of early prototypes, several technology challenges remain, and need to be addressed through circuittechnology co-design [1]. This paper presents a 64Kb RRAM macro supporting: (1) a programmable (1 to 9) number of row-accesses (N) to enable vector-matrix multiplication (referred to as compute-in-memory, or CIM) for a target algorithm-level

👥 作者与机构

Jong-Hyeok Yoon1, Muya Chang1, Win-San Khwa2, Yu-Der Chih3,

Meng-Fan Chang2, Arijit Raychowdhury1 Georgia Institute of Technology, Atlanta, GA TSMC Corporate Research, Hsinchu, Taiwan 3 TSMC Design Technology, Hsinchu, Taiwan 1 2 As