A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

📋 论文概要

本文提出了一种K波段12.1-16.6GHz子采样全数字锁相环（ADPLL），采用随机闪存时间数字转换器（TDC）和耦合双核DCO，实现了47.3fsrms的极低抖动，旨在满足大规模MIMO和数字波束成形等复杂远程射频头端的需求。

💡 主要创新点

• 采用随机闪存TDC实现高分辨率时间量化，降低量化噪声。
• 通过耦合双核DCO结构改善相位噪声和调谐范围。
• 子采样架构结合数字域处理，实现低抖动和高能效频率合成。

🏷 关键词

📄 原文摘要

Sergey Bershansky2, Nir Geron2, Ashoke Ravi3, Rotem Banin2, Jasmin Kadry2, Gil Horovitz2, Christian Krassnitzer1, Christoph Duller1, Patrick Torta1, Mark Elzinga4, Kamran Azadet5 Intel, Villach, Austria Intel, Israel, Israel 3 Intel, Hillsboro, OR 4 Intel, Folsom, CA 5 Intel, Santa Clara, CA 1 2 The demand for massive MIMO, digital beamforming, and increased bandwidth communication dramatically increases the complexity of the remote radio head in future cellular base-stations. This complexity issue can be addressed by RF transceiver SoCs incorporating multiple direct RF radio transceivers, which have clear advantages over conventional architectures and are enabled by high-performance digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). However, the sampling clock for these high-performance data converters must fulfill very stringent in-band and outof-band spectral mask requirements, which are hard to meet with RF frequency

👥 作者与机构

Edwin Thaller1, Run Levinger2, Evgeny Shumaker2, Aryeh Farber2,