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ISSCC 2019Session 6 · ULTRA-HIGH-SPEED WIRELINEWireline I/O7nm FinFET

A 180mW 56Gb/s DSP-Based Transceiver for HighDensity IOs in Data Center Switches in 7nm FinFET Technology

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📋 论文概要

该论文提出了一种基于DSP的56Gb/s收发器,采用7nm FinFET工艺,功耗仅180mW,旨在满足数据中心交换机对高密度IO的需求,解决了高速数据传输中的功耗和面积限制问题。

💡 主要创新点

核心指标
56Gb/s数据率,180mW功耗
工艺节点
7nm FinFET
重要性
发表年份
ISSCC 2019

🏷 关键词

56Gb/sDSP收发器高密度IO数据中心交换机7nm FinFET

📄 原文摘要

Po-Shuan Weng2, Yi-Chieh Huang2, Chun-Cheng Liu2, Chien-Hua Wu2, Shih-Hao Huang2, Chungshi Lin2, Ke-Chung Wu2, Kun-Hung Tsai2, Kai-Wen Tan2, Ahmed ElShater1, Kuang-Ren Chen2, Wei-Hao Tsai2, Huan-Sheng Chen2, Weiyu Leng1, Mazen Soliman1 MediaTek, Irvine, CA MediaTek, Hsinchu, Taiwan *Equally-Credited Authors (ECAs) 1 2 A soaring amount of data transfer has been witnessed in recent years. By 2020, 50 billion connected devices are expected, which will generate more than 2 zettabytes of data traffic annually. Given the constraints in power & space, this explosive growth puts high stress on network infrastructure, which demands low power, high BW, and area efficient transceivers. To improve BW efficiency, modern transceivers use PAM-4 instead of NRZ to double the throughput in the same BW. However, PAM-4 introduces substantial ISI, reduces peak-to-averageratio, and imposes non-linearity constraints compared to NRZ modulation. Scaling

👥 作者与机构

Tamer Ali1, Ramy Yousry*1, Henry Park*1, Ehung Chen*1,

分类:Wireline I/O · 年份:ISSCC 2019