ISSCC 2019
Session 1
Plenary
Intelligence on Silicon: From Deep-Neural-Network Accelerators to Brain Mimicking AI-SoCs
lifestyle of all society. AI technology is widely used in most information hardware, software, and networking, underlying all consumer technology: smartphones, home appliances, and the Web. Figure 1.2.1 shows 3 main appl
ISSCC 2019
Session 1
Plenary
Integration of Photonics and Electronics
photonic integrated circuits (PICs) is rapidly growing. Photonic integration which is now the dominant technology in high-bandwidth and longdistance telecommunications is increasingly applied to shorter distances within
ISSCC 2019
Session 1
Plenary
5G Wireless Communication: An Inflection Point
The 5G era is upon us, ushering in new opportunities for technology innovation across the computing and connectivity landscape. The advent of the Internet of Things has resulted in the generation of massive amount of dat
ISSCC 2019
Session 10
RF & Wireless
An Energy Measurement Front-End with Integrated In-Situ Background Full System Accuracy Monitoring Including the Current and Voltage Sensors
to determine billable energy consumption. These devices are factory calibrated, and then perform measurement without interruption over their lifetime. Once in the field their accuracy is unknown due to component aging and
ISSCC 2019
Session 10
RF & Wireless
A 22ng/√Hz 17mW MEMS Accelerometer with Digital Noise-Reduction Techniques
Keijiro Mori, Naoki Mori, Akira Matsumoto, Hideto Kazama, Yudai Kamada, Atsushi Isobe, Tomonori Sekiguchi Hitachi, Tokyo, Japan In emerging applications such as next-generation oil and gas exploration and infrastructure
ISSCC 2019
Session 10
RF & Wireless
A 0.12mm2 Wien-Bridge Temperature Sensor with 0.1°C (3σ) Inaccuracy from -40°C to 180°C
energy efficiency than conventional BJT-based sensors [1], but they typically occupy more area (>0.25mm2) and have lower operating temperatures (≤125°C) [2-4]. This work describes a 0.12mm2 resistor-based sensor that uses
ISSCC 2019
Session 10
RF & Wireless
A Wheatstone Bridge Temperature Sensor with a Resolution FoM of 20fJ·K2
Temperature sensors intended for embedded applications should be both energyand area-efficient. The combination of Wheatstone-bridge (WhB) sensors and continuous-time ADCs has proven to be highly energy efficient [1,2]. Ho
ISSCC 2019
Session 11
Medical & Bio
A 5.37mW/Channel Pitch-Matched Ultrasound ASIC with Dynamic-Bit-Shared SAR ADC and 13.2V Charge-Recycling TX in Standard CMOS for Intracardiac Echocardiography
Institute for Neurotechnology, Singapore, Singapore 1 2 Intracardiac echocardiography (ICE) is an ultrasound sonogram that visualizes the anatomical structure of the heart in real time, with a mm-scale catheter inserted
ISSCC 2019
Session 11
Medical & Bio
A CMOS Biosensor Array with 1024 3-Electrode Voltammetry Pixels and 93dB Dynamic Range
Rituraj Singh1, Nader Gamini1, Davood Shahrjerdi2, Robert G. Kuimelis1, Arjang Hassibi1 InSilixa, Sunnyvale, CA New York University, New York, NY 1 2 Electro-analytical (E-chem) biosensors offer unique advantages over wi
ISSCC 2019
Session 11
Medical & Bio
A Capacitive Biosensor for Cancer Diagnosis Using a Functionalized Microneedle and a 13.7b-Resolution Capacitance-to-Digital Converter from 1 to 100nF
dedicated blood supply to provide oxygen and nutrients. Therefore, vascular endothelial growth factor (VEGF), a signal protein produced by cells stimulating angiogenesis, is considered as a key biomarker in clinical diag
ISSCC 2019
Session 11
Medical & Bio
A Fast-Readout Mismatch-Insensitive Magnetoresistive Biosensor Front-End Achieving Sub-ppm Sensitivity
Magnetic biosensors have drawn significant research interest as a means to replace large optical instrumentation commonly found in centralized diagnostic laboratories. Magnetic biosensing is attractive since biological sa
ISSCC 2019
Session 11
Medical & Bio
A 512-Pixel 3kHz-Frame-Rate Dual-Shank Lensless Filterless Single-Photon-Avalanche-Diode CMOS Neural Imaging Probe
Laurent Moreaux3, Michael L. Roukes3, Kenneth L. Shepard1 Columbia University, New York, NY KIST, Seoul, Korea 3 California Institute of Technology, Pasadena 1 out of Geiger mode after sufficient decay of the fluorescent s
ISSCC 2019
Session 12
Other
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz
Toshinari Watanabe1,2, Hiroaki Honjo1,2, Hiroki Koike1,2, Takashi Nasuno1,2, Yitao Ma1, Takaho Tanigawa1,2, Yasuo Noguchi1,2, Mitsuo Yasuhira1,2, Hideo Sato1, Shoji Ikeda1,2, Hideo Ohno1, Tetsuo Endoh1,2, Takahiro Hanyu1
ISSCC 2019
Session 12
Other
Micro Short-Circuit Detector Including S/H Circuit for 1hr Retention and 52dB Comparator Composed of C-Axis Aligned Crystalline IGZO FETs for Li-Ion Battery Protection IC
Toshihiko Takeuchi1, Kousei Nei1, Takako Seki1, Yuto Yakubo1, Kei Takahashi1, Shuji Fukai1, Takahiko Ishizu1, Munehiro Kozuma1, Ryota Tajima1, Takanori Matsuzaki1, Takayuki Ikeda1, Makoto Ikeda2, Shunpei Yamazaki1 Semico
ISSCC 2019
Session 13
Memory
A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-LineLayer Technology
M. Miakashi1, Y. Nagadomi1, T. Nakano1, T. Kawabe1, T. Shibuya1, M. Sako1, K. Yanagidaira1, T. Hashimoto1, H. Date1, M. Sato1, T. Nakagawa1, H. Takamoto1, J. Musha1, T. Minamoto1, M. Uda1, D. Nakamura1, K. Sakurai1, T. Y
ISSCC 2019
Session 13
Memory
A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V
Tanaya Sahu, Juan Alzate-vinasco, Ajay Vangapaty, Mesut Meterelliyoz, Nathan Strutt, Albert B. Chen, Patrick Hentges, Pedro A. Quintero, Chris Connor, Oleg Golonzka, Kevin Fischer, Fatih Hamzaoglu Intel, Hillsboro, OR A
ISSCC 2019
Session 13
Memory
A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique
Nilanjan Das, Kevin Fischer, Tahir Ghani, Oleg Golonzka, Patrick Hentges, Rawshan Jahan, Pulkit Jain, Blake Lin, Mesut Meterelliyoz, Jim O’Donnell, Conor Puls, Pedro Quintero, Tanaya Sahu, Meenakshi Sekhar, Ajay Vangapat
ISSCC 2019
Session 13
Memory
A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface In this work, to minimize the capacitive coupling between WLN and WLN+1, we
for the verify operations. Dongku Kang, Minsu Kim, Su Chang Jeon, Wontaeck Jung, Jooyong Park, Gyosoo Choo, Dong-kyo Shim, Anil Kavala, Seung-Bum Kim, Kyung-Min Kang, Jiyoung Lee, Kuihan Ko, Hyun-Wook Park, Byung-Jun Min
ISSCC 2019
Session 13
Memory
A 512Gb 3-bit/Cell 3D Flash Memory on 128-WordlineLayer with 132MB/s Write Performance Featuring CircuitUnder-Array Technology
Noboru Shibata2, Kapil Verma1, Takuya Ariki1, Jason Li1, Jong Yuh1, Anirudh Amarnath1, Qui Nguyen1, Ohwon Kwon1, Stanley Jeong1, Heguang Li1, Hua-Ling Hsu1, Tai-yuan Tseng1, Steve Choi1, Siddhesh Darne1, Pradeep Anantula
ISSCC 2019
Session 14
AI / ML
A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics
Artificial swarm intelligence, inspired by biological studies of insects, ants and other organisms, present an emerging computing paradigm, where seemingly simple elements interact with each other to collectively solve ch
ISSCC 2019
Session 14
AI / ML
A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration
factors in the energy and performance of both general purpose CPUs and GPUs. This has led to extensive research focused on in-memory computing, which moves computation to where the data is located. With this approach, co
ISSCC 2019
Session 14
AI / ML
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7µs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques
William Hwang1, Seungbin Jeong1, Haitong Li1, Pulkit Tandon1, Elisa Vianello2, Pascal Vivet2, Etienne Nowak2, Mary K. Wootters1, H.-S. Philip Wong1, Mohamed M. Sabry Aly3, Edith Beigne2, Subhasish Mitra1 Stanford Univers
ISSCC 2019
Session 14
AI / ML
All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing
Convolutional Neural Networks (CNN) provide superior classification accuracy in a variety of machine learning applications, such as image/speech/sensor data processing. However, CNNs require intensive compute and memory r
ISSCC 2019
Session 14
AI / ML
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
University of Washington, Seattle, WA Low-Dropout Regulators (LDOs) play an important role in enabling fine-grained supply-voltage domains for energy-efficient SoC design [1]. Digital LDOs are of particular interest due to
ISSCC 2019
Session 14
AI / ML
A 745pA Hybrid Asynchronous Binary-Searching and Synchronous Linear-Searching Digital LDO with 3.8×105
Shuo Li, Benton H. Calhoun University of Virginia, Charlottesville, VA Voltage regulators for emerging nW-to-μW Internet-of-Things (IoT) systems-onchip (SoCs) require ultra-low quiescent power to enhance lifetime, a larg
ISSCC 2019
Session 14
AI / ML
A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation
Khondker Z. Ahmed, Krishnan Ravichandran, James Tschanz, Vivek De Intel, Hillsboro, OR Complex SoCs in scaled CMOS processes integrate a large variety of digital, SRAM and noise-sensitive mixed-signal/analog circuit bloc
ISSCC 2019
Session 15
Wireless
An 88%-Efficiency Supply Modulator Achieving 1.08μs/V Fast Transition and 100MHz Envelope-Tracking Bandwidth for 5G New Radio RF Power Amplifier
Jeonghyun Choi, Takahiro Nomiyama, Jaeyeol Han, Younghwan Choo, Yongsik Youn, Euiyoung Park, Sungjun Lee, Ik-Hwan Kim, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang Samsung Electronics, Hwaseong, Korea In the recent 3GPP
ISSCC 2019
Session 15
Wireless
A 90ns/V Fast-Transition Symbol-Power-Tracking Buck Converter for 5G mm-Wave Phased-Array Transceiver
(mm-wave) bands requires a low-cost antenna module consisting of a phased-array transceiver with beamforming [1], an antenna array, and a power management IC (PMIC). Since a typical on-chip mm-wave CMOS power-amplifier (P
ISSCC 2019
Session 15
Wireless
A 100W and 91% GaN-Based Class-E Wireless-PowerTransfer Transmitter with Differential-ImpedanceMatching Control for Charging Multiple Devices
devices charged by a wireless-power-transfer (WPT) system has become more common as illustrated in Fig. 15.3.1. A wide-power-range (no load ~100W), compact, and efficient WPT system needs to include the following features
ISSCC 2019
Session 15
AI / ML
A 52% Peak-Efficiency >1W Isolated Power Transfer System Using Fully Integrated Magnetic-Core Transformer
wide field of applications to guarantee human safety or better reliability in harsh industrial environments. The transfer of both data and power across an isolation barrier is often an essential requisite in these applica
ISSCC 2019
Session 15
Wireless
An 800mW Fully Integrated Galvanic Isolated Power Transfer System Meeting CISPR 22 Class-B Emission Levels with 6dB Margin
automation systems. Employing galvanic isolation in the transceivers of such networks has become an essential requisite to guarantee safety and better reliability in harsh industrial environment. For industrial transceiv
ISSCC 2019
Session 15
Wireless
A 10MHz i-Collapse Failure Self-Prognostic GaN Power Converter with TJ-Independent In-Situ Condition Monitoring and Proactive Temperature Frequency Scaling
With superior figure of merits, GaN switchs are highly anticipated to replace MOSFETs in high-performance power circuits [1,2]. However, GaN technology today still faces formidable reliability challenges [3]. While GaN de
ISSCC 2019
Session 15
Wireless
An 8.3MHz GaN Power Converter Using Markov Continuous RSSM for 35dBμV Conducted EMI Attenuation and One-Cycle TON Rebalancing for 27.6dB VO Jittering Suppression
GaN power switches have gained fast-growing popularity in power electronics. With a similar RDS_ON resistance, they boast 2-to-3-order lower gate capacitance than silicon counterparts, making them highly desirable in hig
ISSCC 2019
Session 15
Wireless
A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs
Active gate control is an emerging technique to minimize the switching loss of highpower converters facing noise-suppression challenges. In a conventional gate-driver design, a fixed value of gate resistance is chosen by
ISSCC 2019
Session 16
Clocking & PLLs
A 265µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS
exponentially increased for Systems on Chip (SoC). A fractional-N phase-locked loop (PLL) is one of the most important building blocks in SoCs for a variety of applications, such as frequency synthesis for wireless trans
ISSCC 2019
Session 16
Clocking & PLLs
A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization
have ultra-low phase noise (PN) is very important for the design of RF transceivers (TRXs) for high-data-rate 5G systems. Direct-RF-sampling TRXs also require high-frequency clock signals, having extremely low integrated
ISSCC 2019
Session 16
Clocking & PLLs
A -246dB Jitter-FoM 2.4GHz Calibration-Free RingOscillator PLL Achieving 9% Jitter Variation Over PVT
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Low-jitter phase-locked loops (PLLs) are critical building blocks in various systems, including wireless and wireline communications and ADCs. LC osci
ISSCC 2019
Session 16
Clocking & PLLs
A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation
There is need for a low-power, compact, means of generating multiple, low-jitter, spectrally pure, clock signals at different frequencies using a single reference oscillator, both in wireline and wireless applications, o
ISSCC 2019
Session 16
Clocking & PLLs
A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax
11ax WLAN standard improves the throughput by supporting 1024-QAM in a channel bandwidth of 160MHz, demanding extremely low jitter values for the transmitter (Tx) and the receiver (Rx) synthesizers. Recent work has achie
ISSCC 2019
Session 16
Clocking & PLLs
A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and -70dBc Fractional Spurs
standards, such as WiFi 802.11ax with a 1024-QAM mode, require RF clocks with extremely low integrated phase error and low spurs. Because of their good scalability, digital phase-locked loops (DPLLs) have been widely stu
ISSCC 2019
Session 16
Clocking & PLLs
A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS
Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino Politecnico di Milano, Milan, Italy Digital phase-locked loops (DPLLs) have been demonstrated to achieve excellent performance as fractional-N fr
ISSCC 2019
Session 16
Clocking & PLLs
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur
Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Recent mm-wave PLLs have explored different architectures to enhance their jitter performance at l
ISSCC 2019
Session 16
Clocking & PLLs
GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur
Stefano Tulisi4, Sanganagouda Patil4, Ciarán Curtin4, Stephen Brookes4, Brian Shelly4, Patrick Griffin4, Michael Keaveney4 University College Dublin, Dublin, Ireland Microelectronic Circuits Centre Ireland, Dublin, Irelan
ISSCC 2019
Session 17
Medical & Bio
AI x Robotics: Technology Challenges and Opportunities
(AI) was first used. In those days it was also called as symbolic AI (Symbolic-AI) [1]. For example, let us assume a block world problem in Fig 17.1.1 (right), where a block is represented as a symbol, “Block1”, and it ca
ISSCC 2019
Session 17
Medical & Bio
A 142nW Voice and Acoustic Activity Detection Chip for mm-Scale Sensor Nodes Using Time-Interleaved MixerBased Frequency Scanning
one of the most widely used sensing modalities to intelligently assess the environment. In particular, ultra-low power (ULP) always-on voice activity detection (VAD) is gaining attention as an enabling technology for IoT
ISSCC 2019
Session 17
Medical & Bio
Hybrid System for Efficient LAE-CMOS Interfacing in Large-Scale Tactile-Sensing Skins via TFT-Based Compressed Sensing
Sigurd Wagner, James C. Sturm, Naveen Verma Princeton University, Princeton, NJ *Equally-Credited Authors (ECAs) Tactile sensing has wide-ranging applications, from intelligent surfaces to advanced robotics. Large-Area E
ISSCC 2019
Session 17
Medical & Bio
16MHz FRAM Micro-Controller with a Low-Cost Sub-1μA Embedded Piezo-Electric Strain Sensor for ULP Motion Detection
Nagaraj Krishnasawamy1, Hadi Najar2, Suman Bellary2, Wei-Yan Shih1, Scott Summerfelt1, Steven Bartling1 Texas Instruments, Dallas, TX Texas Instruments, Santa Clara, CA 1 2 Ultra-low Power Microcontrollers (MCUs) [1-4] h
ISSCC 2019
Session 17
Medical & Bio
A 0.8mm3 Ultrasonic Implantable Wireless Neural Recording System with Linear AM Backscattering
Sina Faraji Alamouti, Cem Yalcin, Benjamin C. Johnson, Jose M. Carmena, Michel M. Maharbiz, Rikky Muller University of California, Berkeley, CA Miniaturization of implantable neural recording systems to micron-scale volu
ISSCC 2019
Session 17
Medical & Bio
A Sub-40µW 5Mb/s Magnetic Human Body Communication Transceiver Demonstrating Trans-Body Delivery of High-Fidelity Audio to a Wearable In-Ear Headphone
Emerging wearable devices such as wireless headphones, smart glasses, and medical monitors require increasingly high-throughput wireless communications at ultra-low-power. Since far-field RF has significant path loss aroun
ISSCC 2019
Session 17
Medical & Bio
A 7.0fps Optical and Electrical Dual Tomographic Imaging SoC for Skin-Disease Diagnosis System
million cases of skin cancer were treated in over 3.3 million people in the U.S. in 2012, and more people are diagnosed with skin cancer each year than all other cancers combined in the U.S. [1]. Because a malignant lesi
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