Cosimo Aprile1,2, Thomas Morf2, Marcel Kossel2, Alessandro Cevrero2, Ilter Ozkaya1,2, Andreas Burg1, Thomas Toifl2, Yusuf Leblebici1 EPFL, Lausanne, Switzerland IBM Zurich Research Laboratory, Rueschlikon, Switzerland 3 *now with KAIST, Daejeon, Korea 4 ETH Zürich, Zurich, Switzerland 5 IBM T. J. Watson Research Center, Yorktown Heights, NY 1 2 The increasing demand on bandwidth for communicating among processors through wired interconnects in large-scale servers motivates the increase in the lane-data-rate from the current 28Gb/s to 56Gb/s or further. Recently published works [1-3] demonstrated ADC-based receiver (RX) prototypes equalizing >56Gb/s PAM-4 symbols for legacy channels with pre-FEC BERs of less than 2E4 satisfying IEEE p802.bj/bs pre-FEC BER requirements. While the ADC-based >56Gb/s PAM-4 RXs provide strong equalization performance using a large number of feed-forward equalization (FFE) taps and a few decision-feedback
Gain Kim1,2,3, Lukas Kull2, Danny Luu2,4, Matthias Braendli2,
Christian Menolfi2, Pier-Andrea Francese2, Hazar Yueksel5,