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ISSCC 2019Session 30 · ADVANCED WIRELINE TECHNIQUESWireline I/O28nm FDSOI

A 32Gb/s 2.9pJ/b Transceiver for Sequence-Coded PAM-4 Signalling with 4-to-6dB SNR Gain in 28nm FDSOI CMOS

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📋 论文概要

该论文提出了一种用于序列编码PAM-4信令的收发器,在28nm FDSOI工艺下实现了32Gb/s的数据率和2.9pJ/b的能效。通过结合序列编码和线性均衡,相比传统PAM-4获得了4-6dB的SNR增益,解决了多电平信令信噪比下降的问题。

💡 主要创新点

核心指标
32Gb/s, 2.9pJ/b, 4-6dB SNR gain
工艺节点
28nm FDSOI
重要性
发表年份
ISSCC 2019

🏷 关键词

序列编码PAM-4低功耗收发器SNR增益28nm FDSOI

📄 原文摘要

Intel, Santa Clara, CA 1 2 Multilevel signaling such as PAM-4 makes more efficient use of the better part of the channel response by mapping multiple bits in the same time interval (i.e. UI). At the same time, to achieve lower power consumption simple equalization techniques such as TX-FIR and RX peaking equalization are often preferred. For example, in Fig. 30.4.1, a channel with 30dB of loss is equalized using these linear equalization techniques. However, the increased spectrum efficiency comes at the cost of SNR that is captured in the single bit response (SBR). Here, the equalized symbol response can be decomposed into MSB and LSB SBRs. In PAM-4 signaling, individual eye heights are set by the LSB SBR, whereas, the total signal amplitude is set by the MSB and LSB combined SBR. This 1/3 ratio suggests a 9dB SNR penalty, but in reality, crosstalk and residual ISI noise also get enhanced.

👥 作者与机构

Aurangozeb1, Carson Dick1, Maruf Mohammad2, Masum Hossain1

University of Alberta, Edmonton, Canada

分类:Wireline I/O · 年份:ISSCC 2019