Digital Leakage Compensation for a Low-Power and LowJitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology

📋 论文概要

该论文针对10nm FinFET工艺中模拟PLL因泄漏电流导致的静态相位误差、抖动和参考杂散问题，提出了一种数字泄漏补偿技术。实现了0.5-5GHz宽带低功耗低抖动PLL，在消除泄漏影响的同时保持低功耗和低抖动特性。

💡 主要创新点

• 提出数字泄漏补偿方法，有效抑制泄漏电流引起的静态相位误差和抖动，无需大幅增加功耗。
• 在10nm FinFET工艺中实现了0.5-5GHz的宽频率范围PLL，兼顾低功耗与低抖动性能。
• 相比传统数字PLL，避免了高功耗和高量化噪声问题，同时保留模拟PLL的低抖动优势。

🏷 关键词

📄 原文摘要

loop (PLL) design [1] continues in the 10nm node and beyond, the leakage from various sources could become an issue in the applications where the reference clock frequency is low and the static phase error is required to be close to zero at all process corners and temperatures. The impacts of leakage currents on analog PLLs are the increase of static phase error, higher jitter and reference spur. To mitigate the leakage sensitivity in analog PLL designs, digital PLLs have been designed [2-3], but they often exhibit higher power consumption and higher jitter due to quantization noise, and require high-performance voltage regulators or supply-noise cancellation techniques [4] due to their high sensitivity to powersupply noise. To compensate for the leakage current in analog PLLs, analog

👥 作者与机构

Yongping Fan, Bo Xiang, Dan Zhang, James S. Ayers,

Kuan-Yueh James Shen, Andrey Mezhiba Intel, Hillsboro, OR As the push for low-power, low-jitter, and low-area phase-locked