A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

📋 论文概要

该论文提出了一种基于Twin-8T SRAM的计算内存宏单元，用于多比特卷积神经网络（CNN）的机器学习，通过将乘法累加操作融入SRAM阵列，显著提升了能效。

💡 主要创新点

• 提出了一种新型Twin-8T SRAM单元结构，支持多位宽数据的计算内存操作，避免了传统模拟计算中的精度损失。
• 设计了专用的计算内存宏单元架构，能够高效执行多比特CNN的乘加运算，减少了数据搬运能耗。

🏷 关键词

📄 原文摘要

Jing-Hong Wang1, Yen-Cheng Chiu1, Wei-Chen Wei1, Ssu-Yen Wu1, Xiaoyu Sun3, Rui Liu3, Shimeng Yu4, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Qiang Li2, Meng-Fan Chang1 National Tsing Hua University, Hsinchu, Taiwan University of Electronic Science and Technology of China, Chengdu, China 3 Arizona State University, Tempe, AZ 4 Georgia Institute of Technology, Atlanta, GA 1 2 Computation-in-memory (CIM) is a promising avenue to improve the energy efficiency of multiply-and-accumulate (MAC) operations in AI chips. Multi-bit CNNs are required for high-inference accuracy in many applications [1-5]. There are challenges and tradeoffs for SRAM-based CIM: (1) tradeoffs between signal margin, cell stability and area overhead; (2) the high-weighted bit process variation dominates the end-result error rate; (3) trade-off between input bandwidth, speed and area. Previous SRAM CIM macros were limited to binary

👥 作者与机构

Xin Si1,2, Jia-Jing Chen1, Yung-Ning Tu1, Wei-Hsing Huang1,