An 8×-OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT ΔΣ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS

📋 论文概要

本文提出了一种采用7位线性化分段DAC和数字噪声耦合技术的连续时间ΔΣ调制器，在8倍过采样率下实现了25MHz带宽和79.4dB/74dB的DR/SNDR性能，解决了低OSR下保持高动态范围的难题。

💡 主要创新点

• 使用7位线性化分段DAC降低非线性失真，支持低OSR下的高分辨率量化。
• 引入数字噪声耦合技术进一步抑制量化噪声，提升SNDR。
• 在8倍低OSR下实现宽带高动态范围，适合低功耗蜂窝接收前端。

🏷 关键词

📄 原文摘要

block in a cellular receiver design. A continuous-time delta-sigma modulator (CTDSM), which gets the benefit of inherent anti-alias filtering, is a common architecture choice for the ADC. However, low power dissipation dictates a low over-sampling ratio (OSR) since the bandwidth of the loop filter, DAC switching rate, and the clock frequency of the subsequent digital front-end are all proportional to the sampling frequency. Due to the desire for low OSR, a higher quantization level is required to maintain dynamic range, and the successive approximation register (SAR) quantizer, which gets the benefits of power and area efficiency compared to a flash quantizer, becomes more attractive in nanometer processes. However, the issue with a SAR quantizer in a high-speed CTDSM is

👥 作者与机构

Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Ting-Yang Wang,

Yun-Shiang Shu, Pao-Cheng Chiu MediaTek, Hsinchu, Taiwan A low-power and high-dynamic-range downlink ADC is the most critical building