A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors increasing the duty cycle to ~100% and maximizing the time for enabling the high side of the output stage. On the contrary, if FOUT speeds up with respect to FREF due to a large VOUT overshoot event, the duty cycle may reduce to ~0%, minimizing the time the high side of the output stage is enabled.

📋 论文概要

该论文提出了一种基于高带宽两相降压转换器的全数字统一电压和频率调节器（UVFBR），采用7nm工艺实现。通过TRC振荡器实现输出电压与输出频率的相互依赖关系，并利用可配置延迟校准振荡器周期以匹配数字负载的关键路径延迟，解决了传统模拟调节器在先进工艺下的集成难题。

💡 主要创新点

• 提出全数字架构的统一电压和频率调节器，无需模拟补偿网络，适合先进工艺缩放。
• 采用高带宽两相降压转换器，结合TRC振荡器实现电压与频率的协同调节，提高瞬态响应。
• 通过可配置延迟校准机制，使振荡器周期精确匹配处理器关键路径延迟，优化能效。

🏷 关键词

📄 原文摘要

Daniel Yingling1, Yu Sun1, Brad Appel1, Anthony Polomik1, Mahesh Harinath1, Joshua Morelli1, Thomas Moore1, Nathaniel Reeves2, Amer Cassier2, Arijit Raychowdhury3 The TRC oscillator enables the interdependent relationship between VOUT and FOUT in the UVFBR. The TRC contains configurable delays to calibrate the oscillator clock period to match the critical-path delay of the digital load (i.e., processor). Each coarse tuning-bit (Coarse_s[3:0]) adjusts the TRC oscillator cycle time by ~30ps, and each small-tuning bit (S[0:12]) adjusts the TRC oscillator by ~4ps resulting in a worst-case timing inaccuracy of ~1.0% at 3.0Ghz. The performance counters allow an on-die measurement of FOUT, which is scanned out of the chip to capture the TRC oscillator frequency. The UVFBR can operate in single-phase mode by either asserting phase1a_select or phase1b_select or in 2-phase mode by asserting both signals. Six

👥 作者与机构

Francois Atallah1, Keith Bowman1, Hoan Nguyen1, Jihoon Jeong1,