An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GeneralPurpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution

📋 论文概要

该论文提出一种自适应时钟管理方案，通过利用指令级动态时序松弛（DTS）来优化通用图形处理器的频率调节，解决了传统DVFS粒度不足和Razor技术需要额外电路的问题。

💡 主要创新点

• 提出基于指令的动态时序松弛利用方法，实现周期级自适应时钟管理。
• 无需额外错误检测电路，通过指令特征预测时序松弛，提高能效。

🏷 关键词

📄 原文摘要

Cycle-by-cycle dynamic timing slack (DTS), which represents extra timing margin from the critical-path timing slack reported by the static timing analysis (STA), has been observed at both program level and instruction level. Conventional dynamic voltage and frequency scaling (DVFS) works at the program level and does not provide adequate frequency-scaling granularity for instruction-level timing management [1]. Razor-based techniques leverage error detection to exploit the DTS on a cycle-bycycle basis [2]. However, it requires additional error-detection circuits and architecture-level co-design for error recovery [3]. Supply droop-based adaptive clocking was used to reduce timing margin under PVT variation, but does not address the instruction-level timing variation [4]. Recently, instruction-based adaptive clock schemes have been introduced to enhance a CPU’s operation [5-6]. For example,

👥 作者与机构

Tianyu Jia, Russ Joseph, Jie Gu

Northwestern University, Evanston, IL