⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一款采用7nm CMOS工艺的60Gb/s PAM-4 ADC-DSP收发器，通过基于信噪比的自适应功率缩放技术，在32dB信道损耗下实现了6.9pJ/b的能效，解决了高速PAM-4信号传输中功耗效率与性能平衡的问题。
Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto Huawei Technologies, Ottawa, ON, Canada With the introduction of PAM-4 signaling at 56Gb/s and the decreased benefits of CMOS scaling for high-speed mixed-signal designs, SerDes designers and system architects are faced with severe performance versus power budget constraints. Power management and energy efficiency have become the main drivers for system design. However, industry standards such as EEE have failed to keep up with efficiency demands. In this context the choice between a so-called analog mixed signal (AMS) SerDes architecture vs. an ADC-DSP-based one has been debated at length. AMS provides significantly lower maximum power [2,4] while ADC-DSP provides higher link margin [1] thus avoiding expensive and power hungry repeater ICs that largely negate the power advantage of AMS
Marc-Andre LaCroix, Henry Wong, Yun Hua Liu, Huong Ho,