A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a

📋 论文概要

该论文提出了一款采用1.1V 1ynm工艺的16Gb DDR5 SDRAM，支持6.4Gb/s/pin数据速率。通过引入相位旋转器DLL、高速SerDes和RX/TX均衡方案，并优化写训练流程，实现了低功耗和高采样保持性能。

💡 主要创新点

• 提出了基于相位旋转器的DLL设计，改善了时钟抖动和相位控制精度。
• 采用了高速SerDes和RX/TX均衡方案，支撑6.4Gb/s/pin高数据速率。
• 优化了写训练流程，通过精细扫描DQS信号匹配IWES上升沿，省去额外延迟电路，降低功耗并改善采样保持特性。

🏷 关键词

📄 原文摘要

write (MRW) setting. 3rd step is fine training, sweeping the DQS signal to find the rising edge of IWES. After the training, IWES and DQS are matched without any additional delay. Therefore, it saves the power consumption of DQ/DQS delay and improves S/H characteristics. Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyungwhan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong Uk Lee, Jaein Lee, Daesuk Kim, Kihun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jongsam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh For high-density servers a main memory should support multiple modules and have multi-drop topology. A multi-drop topology induces ISI noise from reflections and it is a bottleneck to increase interface speed. In the DDR5 SDRAM,

👥 作者与机构

Phase-Rotator-Based DLL, High-Speed SerDes and, RX/TX Equalization Scheme