A 256×256 40nm/90nm CMOS 3D-Stacked 120dBDynamic-Range Reconfigurable Time-Resolved SPAD Imager

📋 论文概要

本文提出了一种256×256分辨率的3D堆叠CMOS SPAD图像传感器，采用40nm/90nm工艺，实现了120dB动态范围的可重构时间分辨成像，解决了LIDAR应用中因距离、反射率和太阳背景光造成的极端动态范围挑战。

💡 主要创新点

• 采用3D堆叠技术将SPAD像素阵列与读出电路垂直集成，提高填充因子和性能
• 实现可重构的时间分辨成像架构，支持高动态范围（120dB）的LIDAR信号检测
• 在40nm/90nm异质工艺节点上实现了256×256大规模SPAD阵列的集成

🏷 关键词

📄 原文摘要

Kingdom 3 Heriot-Watt University, Edinburgh, United Kingdom 1 2 Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to laser returns affected by the inverse square law over 2-3 decades of distance, diverse target reflectivity, and high solar background [1]. Integrated CMOS SPADs have a native DR exceeding 140dB, typically extending from the noise floor of few cps to 100’s Mcps peak rate. To deliver this DR to downstream DSP, large SPAD time-resolved imaging arrays must count and time billions of single photon events per second demanding massively parallel on-chip pixel processing to achieve practical I/O power consumption and data rates. Hybrid Cu-Cu bonding offers a

👥 作者与机构

Robert K. Henderson1, Nick Johnston1, Sam W. Hutchings1,

Istvan Gyongy1, Tarek Al Abbas1, Neale Dutton2, Max Tyler3, Susan Chan3, Jonathan Leach3 University of Edinburgh, Edinburgh, United Kingdom STMicroelectronics, Edinburgh, United