A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation

📋 论文概要

该论文提出一种采用14nm CMOS工艺的模块化混合低压差稳压器（LDO），通过动态钳位调谐技术实现了快速负载瞬态响应和可编程电源抑制比（PSRR），解决了复杂SoC中不同模块对供电电压快速稳定和噪声隔离的需求。

💡 主要创新点

• 提出模块化混合LDO架构，融合数字和模拟LDO优势，兼顾快速响应和低功耗。
• 引入动态钳位调谐技术，实现可编程PSRR，适应不同噪声敏感度模块。
• 在14nm CMOS工艺中实现，具备宽工作范围和高能效。

🏷 关键词

📄 原文摘要

Khondker Z. Ahmed, Krishnan Ravichandran, James Tschanz, Vivek De Intel, Hillsboro, OR Complex SoCs in scaled CMOS processes integrate a large variety of digital, SRAM and noise-sensitive mixed-signal/analog circuit blocks such as PLLs, wireline/wireless/RF transceivers, sensor front-ends, etc. The on-die low-dropout regulators (LDO) used for fine-grain DVFS of digital and memory blocks must respond fast to large load transients to minimize voltage droops/overshoots without using large decoupling caps, while minimizing power overheads over a wide operating range. The noise-sensitive analog circuits, on the other hand, need LDOs that provide sufficiently high power supply rejection (PSR) and minimal output voltage ripple, while maximizing current efficiency. Fast and scalable digital (DLDO) [1], analog-assisted digital (AA-DLDO) [2-3] and hybrid (HLDO) [4] analog-digital LDOs targeted for digital and memory blocks, as well as high-PSRR

👥 作者与机构

Xiaosen Liu, Harish K. Krishnamurthy, Taesik Na, Sheldon Weng,