⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一款512Gb容量、3-bit/cell（TLC）的3D NAND闪存芯片，采用128个字线层和电路位于阵列下方（CUA）技术，实现了132MB/s的写入性能。解决了高容量3D NAND中字线层数增加带来的性能挑战，通过CUA技术优化了芯片面积和信号路径。
Noboru Shibata2, Kapil Verma1, Takuya Ariki1, Jason Li1, Jong Yuh1, Anirudh Amarnath1, Qui Nguyen1, Ohwon Kwon1, Stanley Jeong1, Heguang Li1, Hua-Ling Hsu1, Tai-yuan Tseng1, Steve Choi1, Siddhesh Darne1, Pradeep Anantula1, Alex Yap1, Hardwell Chibvongodze1, Hitoshi Miwa1, Minoru Yamashita1, Mitsuyuki Watanabe1, Koichiro Hayashi1, Yosuke Kato1, Toru Miwa1, Jang Yong Kang1, Masatoshi Okumura1, Naoki Ookuma1, Muralikrishna Balaga1, Venky Ramachandra1, Aki Matsuda1, Swaroop Kulkani1, Raghavendra Rachineni1, Pai K. Manjunath1, Masahito Takehara1, Anil Pai1, Srinivas Rajendra1, Toshiki Hisada2, Ryo Fukuda2, Naoya Tokiwa2, Kazuaki Kawaguchi2, Masashi Yamaoka2, Hiromitsu Komai2, Takatoshi Minamoto2, Masaki Unno2, Susumu Ozawa2, Hiroshi Nakamura2, Tomoo Hishida2, Yasuyuki Kajitani2, Lei Lin1 Western Digital, Milpitas, CA Toshiba Memory, Yokohama, Japan 1 2 Advancements in 3D-Flash memory-layer-stacking technology has enabled
Chang Siau1, Kwang-Ho Kim1, Seungpil Lee1, Katsuaki Isobe2,