A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur

📋 论文概要

本文提出了一种25.4-29.5GHz的隔离式亚采样锁相环（SSPLL），功耗仅10.2mW。通过隔离式亚采样技术，实现了-252.9dB的极低抖动功耗优值（FoM）和-63dBc的低参考杂散，解决了高频注入锁相环中杂散大和PVT敏感的问题。

💡 主要创新点

• 提出隔离式亚采样结构，在不引入额外噪声的前提下有效抑制参考杂散。
• 实现低功耗与低抖动的平衡，获得业界领先的抖动功耗优值（FoM）。

🏷 关键词

📄 原文摘要

Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Recent mm-wave PLLs have explored different architectures to enhance their jitter performance at low power. Without noisy loop components, the injection-locked PLL in [1] using a GHz reference (REF=2.25GHz) can effectively suppress the integrated jitter (86fsrms), resulting in a better jitter-power FoM (-247.2dB). Yet, high-frequency REF injection leads to large spur (-32dBc), entailing continuous frequency tracking to withstand the PVT variations. Also, at the system level, the GHz REF has to be generated on-chip (i.e. cascaded PLLs). The power overhead, e.g., additional 20mW in [2], and unwanted coupling between the two VCOs become inevitable. To this end, direct-synthesis mm-wave PLLs using a MHz REF are of higher interest, despite the challenge of a large division ratio (N). An

👥 作者与机构

Zunsong Yang1, Yong Chen1, Shiheng Yang1, Pui-In Mak1,