A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration

📋 论文概要

该论文提出了一种基于SRAM的位串行计算内存架构，支持整数和浮点运算，用于可编程的向量加速。解决了传统模拟内存计算对PVT敏感且需要昂贵ADC/DAC转换的问题。

💡 主要创新点

• 提出数字域位串行计算方式，避免模拟内存计算的PVT敏感性和ADC/DAC开销。
• 支持可编程的整数和浮点运算，提升内存计算灵活性。
• 采用SRAM阵列实现，适合大规模向量加速应用。

🏷 关键词

📄 原文摘要

factors in the energy and performance of both general purpose CPUs and GPUs. This has led to extensive research focused on in-memory computing, which moves computation to where the data is located. With this approach, computation is often performed on the memory bit-lines in the analog domain using current summing [1-3], which requires expensive analog-to-digital and digital-to-analog conversions at the array boundary. In addition, such analog computation is very sensitive to PVT variations, limiting precision. More recently, full-rail (digital) binary in-memory computing was proposed to avoid this conversion overhead and improve robustness [4, 5]. However, both prior in-memory approaches suffer from the same major limitations: they accelerate only one type of algorithm and are inherently restricted to a very

👥 作者与机构

Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan,

Reetuparna Das, David Blaauw, Dennis Sylvester University of Michigan, Ann Arbor, MI Data movement and memory bandwidth are dominant