A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS

📋 论文概要

本文提出一款30GHz分数-N数字锁相环(DPLL)，采用子采样bang-bang相位检测和数字时间转换器(DTC)技术，在65nm LP CMOS工艺中实现198fs rms抖动和35mW功耗，解决了毫米波频段DPLL抖动-功耗折中较差的问题。

💡 主要创新点

• 结合数字时间转换器(DTC)与子采样bang-bang相位检测，实现低抖动分数-N频率合成，适用于毫米波频段。
• 在65nm低功耗CMOS中实现30GHz工作，抖动仅198fs、功耗35mW，达成优异的抖动-功耗权衡。
• 通过数字子采样架构简化环路设计，避免传统模拟PLL的大面积电容和复杂校准。

🏷 关键词

📄 原文摘要

Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino Politecnico di Milano, Milan, Italy Digital phase-locked loops (DPLLs) have been demonstrated to achieve excellent performance as fractional-N frequency synthesizers in the sub-6GHz range, but, when used in the mm-wave range, at 30GHz and above, they typically feature poor jitter-power trade-off. This paper presents a 30GHz fractional-N DPLL in 65nm low-power (LP) CMOS achieving 198fs integrated jitter at 35mW power. The DPLL based on a digital-to-time converter (DTC) combines: (i) sub-sampling bang-bang phase detection to reduce power consumption, (ii) a digital error correction to reduce DTC noise contribution, and (iii) a low-power wide-lock-range divide-bysix circuit to allow operation up to 34GHz. Figure 16.7.1 shows the simplified block diagram of the implemented DPLL. Unlike the fractional-N sub-sampling DPLL introduced in [1], this scheme avoids

👥 作者与机构

Luigi Grimaldi, Luca Bertulessi, Saleh Karman, Dmytro Cherniak,