A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation

📋 论文概要

提出了一种基于数字方法的0.5-2.5GHz多输出分数频率合成器，实现了90fs抖动和-106dBc杂散，解决了多时钟生成中紧凑性和功耗问题。

💡 主要创新点

• 采用全数字架构实现多输出分数频率合成，避免了多PLL复制的面积和功耗开销。
• 通过数字校准技术同时实现了超低抖动和极低杂散性能。
• 支持0.5-2.5GHz宽频率范围和分数分频，适用于多种时钟需求。

🏷 关键词

📄 原文摘要

There is need for a low-power, compact, means of generating multiple, low-jitter, spectrally pure, clock signals at different frequencies using a single reference oscillator, both in wireline and wireless applications, owing to circuit size, cost, and complexity considerations. PLL-based frequency synthesis – analog or digital – can achieve very low jitter and spur levels, but the VCO size and/or power consumption concerns preclude its duplication for multiple on-chip clock generators [1,2]. Open-loop digital methods based on digital-to-phase or digitalto-time converters (DPCs) are compact and employ no power-hungry oscillators, but their circuit errors and mismatches result in strong spurious tones. This paper describes a purely digital spur-cancellation technique that uses a bangbang phase detector (BBPD) and a special noisy, but mostly spur-free, auxiliary clock generator to extract spurious tones precisely and digitally correct for them.

👥 作者与机构

Szu-Yao Hung, Sudhakar Pamarti

University of California, Los Angeles, CA