A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

📋 论文概要

该论文提出了一种基于数字子采样锁相环的28-31GHz频率合成器，实现了76fsrms的抖动和-40dBc的积分相位噪声，解决了毫米波频段低抖动和低相位噪声的难题。

💡 主要创新点

• 采用数字子采样锁相环架构，降低了带内相位噪声，无需高频参考时钟。
• 通过数字控制技术优化了环路带宽和噪声性能，实现了超低抖动和积分相位噪声。

🏷 关键词

📄 原文摘要

have ultra-low phase noise (PN) is very important for the design of RF transceivers (TRXs) for high-data-rate 5G systems. Direct-RF-sampling TRXs also require high-frequency clock signals, having extremely low integrated PN (IPN) [1]. To satisfy such stringent noise requirements, the rms jitter of mmW-band signals must be reduced to sub-100fs. Recently, a charge-pump (CP) PLL in [1] achieved a very low rms jitter of less than 60fs at 14GHz. However, to suppress the in-band PN of PLL building blocks, that design used a reference clock that had an impractically high frequency, fREF, of 500MHz. To avoid the use of such a high fREF while minimizing in-band PN, sub-sampling PLLs (SSPLLs) are seen as a promising solution. However,

👥 作者与机构

Juyeop Kim*, Heein Yoon*, Younghyun Lim*, Yongsun Lee,

Yoonseo Cho, Taeho Seong, Jaehyouk Choi Ulsan National Institute of Science and Technology, Ulsan, Korea *Equally-Credited Authors (ECAs) The generation of mm-wave (mmW) signals that