A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm

📋 论文概要

本文提出了一种6-600MS/s的全动态环形放大器流水线ADC，采用异步事件驱动时钟方案以解决深层流水线中时钟树分布网络带来的寄生、失配和时序偏差问题。通过全动态环形放大器降低功耗，并利用异步时钟简化时序设计，提高了速度与可靠性。

💡 主要创新点

• 提出异步事件驱动时钟方案，免去传统时钟树中复杂的非重叠和因果时序裕度设计，降低功耗和抖动。
• 采用全动态环形放大器作为残差放大器，改善传统流水线中放大器功耗瓶颈问题。
• 支持6-600MS/s宽范围采样率，且无需额外校准或复杂时钟分配网络。

🏷 关键词

📄 原文摘要

critical performance limiter. In “deep” pipelined ADCs that contain many stages, the clock tree constitutes a highly distributed network, with parasitics and mismatch creating skew between the different branches. Sufficient margin must be included in the timing generation such that all non-overlap and causal relationships are maintained. This leads to a difficult set of design tradeoffs in terms of power, speed, jitter, and reliability. Meanwhile, although residue amplifiers have traditionally dominated the power budget in deep pipelines, recent advances such as ring amplification have improved achievable efficiencies to the point that clocking is now the primary consumer in some cases [1,2]. It is already well known that asynchronous event-driven clocking techniques can

👥 作者与机构

Benjamin Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos,

Ewout Martens, Davide Dermit, Jan Craninckx imec, Leuven, Belgium At the upper end of achievable ADC operating speeds, clocking becomes a