A 40-to-80MHz Sub-4µW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with Dual-Loop Adaptive Back-Bias Generator for 20µs Wake-Up From Deep Fully Retentive Sleep Mode

📋 论文概要

本文提出了一款在28nm FDSOI工艺上实现的超低功耗MCU SoC（SleepRunner），采用双环自适应背偏置发生器，在40-80MHz工作频率下实现低于4µW/MHz的功耗和20µs的快速唤醒时间，解决了近阈值电路中速度、功耗与唤醒时间之间的权衡问题。

💡 主要创新点

• 提出双环自适应背偏置发生器，动态调整体偏置以优化PVT变化下的性能与功耗。
• 实现近阈值电压操作下的超低功耗（<4µW/MHz）与快速唤醒（20µs）的平衡。

📄 原文摘要

Pengcheng Xu1, Charlotte Frenkel1, Rémi Dekimpe1, François Stas2, Denis Flandre1 UCLouvain, Louvain-la-Neuve, Belgium e-peas semiconductors, Louvain-la-Neuve, Belgium 1 2 Near-threshold circuits operating at ultra-low voltage (ULV) have matured with integration in commercial products, such as ultra-low-power (ULP) MCUs for the IoT [1]. In this market, MCU design faces the key performance tradeoff between speed, active power, deep-sleep retention power and wakeup time, with the challenge of preserving it over PVT corners. We present a ULP MCU SoC in 28nm FDSOI codenamed SleepRunner, exploiting back-biasing (BB) capability of FDSOI to push the performance tradeoff beyond the state-of-the-art. As shown in Fig. 19.6.1, the MCU logic at 0.4V (VDDL) includes a Cortex-M0 CPU, an FFT accelerator, a wakeup interrupt controller (WIC) and various interfaces. A custom 32KB ULP SRAM [2] is implemented as program memory (PMEM). It

👥 作者与机构

David Bol1, Maxime Schramme1, Ludovic Moreau1, Thomas Haine1,