A 265µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS

📋 论文概要

该论文提出了一款功耗仅265μW的分数-N数字锁相环（DPLL），通过无缝自动切换子采样/采样反馈路径和占空比循环技术，实现了超低功耗运行，解决了以往分数-N DPLL功耗难以低于500μW的问题。

💡 主要创新点

• 提出了一种无缝自动切换子采样/采样反馈路径机制，根据工作模式动态选择最优反馈路径，降低功耗。
• 采用占空比循环技术（Duty-Cycled Fractional-N），进一步减少不必要的电路活动，节省功耗。

🏷 关键词

📄 原文摘要

exponentially increased for Systems on Chip (SoC). A fractional-N phase-locked loop (PLL) is one of the most important building blocks in SoCs for a variety of applications, such as frequency synthesis for wireless transceivers and system clock generation for processors, memories, and I/O interfaces. Recent developments in fractional-N digital PLLs (DPLLs) [1-3] have shown great potential for achieving low-power operation and small chip area. However, none of these works have achieved power consumption below 500μW due to the number of building blocks operating at the oscillator frequency. Furthermore, the digitally controlled oscillators (DCOs) in [1-3] consume more than 250μW of power to achieve a good phase noise and a highenough amplitude for DPLL locking. A digital sub-sampling architecture [1,2,4] can

👥 作者与机构

Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon,

Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada Tokyo Institute of Technology, Tokyo, Japan The demand for highly energy-efficient circuits and systems has