wireline communications has led to emerging standards in the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have demonstrated robust operation over channels with high losses (>20dB) [1], but their power consumption (>500mW/lane excluding DSP) is prohibitive for applications requiring large port counts in short-reach chip-to-chip and chip-to-module links (such as OIF-CEI-112G-VSR/XSR/USR). This work demonstrates a dual PAM-4/NRZ RX implemented in 14nm FinFET and measured up to 100Gb/s in PAM-4 mode achieving pre-FEC BER<10-12 across a 19.2dB-loss channel with low power. To achieve low BER with >16dB loss channel the RX uses a CTLE combined with a 1-tap speculative DFE. To minimize power consumption, the number of slicing levels to resolve the 1-tap PAM-4 DFE
Alessandro Cevrero, Ilter Ozkaya, Pier Andrea Francese, Matthias Brandli,
Christian Menolfi, Thomas Morf, Marcel Kossel, Lukas Kull, Danny Luu, Martino Dazzi, Thomas Toifl IBM Research, Ruschlikon, Switzerland The growing demand for higher data rates in