Computationally Enabled Total Energy Minimization Under Performance Requirements for a VoltageRegulated 0.38-to-0.58V Microprocessor in 65nm CMOS

📋 论文概要

该论文提出了一种计算辅助的总能量最小化方法，能够在满足性能要求的前提下，通过自适应调节供电电压和时钟频率，跟踪最小能量点（MEP），以降低超低功耗集成电路的总能耗。该方法解决了传统方法无法同时控制频率和追踪PVT与活动性变化下MEP的问题。

💡 主要创新点

• 提出一种基于计算的总能量最小化策略，在性能约束下同时调节电压和频率，实现动态能量与泄漏能量的最佳平衡。
• 能够实时追踪对工艺、电压、温度（PVT）和开关活动性敏感的最小能量点（MEP），克服了传统固定频率方法的局限性。

🏷 关键词

📄 原文摘要

University of Washington, Seattle, WA Integrated circuits for ultra-low-power applications strive to minimize total system energy, while satisfying performance requirements. The supply voltage (Vdd) can be set to a Minimum Energy Point (MEP) [1,2], where leakage and dynamic energy are suitably balanced. However, controlling operating frequency (fclk), while concurrently tracking a MEP sensitive to PVT and switching activity is not possible. Meanwhile, the traditional approach of locking to the minimum required frequency (ftarg), and adjusting Vdd to maintain timing slack precludes the possibility of minimum-energy computing. Therefore, there exists a need for a minimum-energy computing architecture that meets performance requirements. Prior work has demonstrated MEP tracking across PVT and switching activity variation [3]. The approach relies on large capacitors for sample-and-hold operation at sub-threshold frequencies, and cannot account for the significant

👥 作者与机构

Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe