A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface In this work, to minimize the capacitive coupling between WLN and WLN+1, we

📋 论文概要

本文介绍了一款512Gb容量、3位/单元的第六代3D V-NAND闪存芯片，实现了82MB/s的写入吞吐量和1.2Gb/s的接口速度，解决了大容量存储中的高吞吐量和高速数据传输问题。

💡 主要创新点

• 采用第六代3D V-NAND技术，提升存储密度和可靠性。
• 实现3-bit/cell（TLC）操作，在512Gb容量下达到82MB/s写入吞吐量。
• 提供1.2Gb/s的高速接口，满足高端存储需求。

🏷 关键词

📄 原文摘要

for the verify operations. Dongku Kang, Minsu Kim, Su Chang Jeon, Wontaeck Jung, Jooyong Park, Gyosoo Choo, Dong-kyo Shim, Anil Kavala, Seung-Bum Kim, Kyung-Min Kang, Jiyoung Lee, Kuihan Ko, Hyun-Wook Park, Byung-Jun Min, Changyeon Yu, Sewon Yun, Nahyun Kim, Yeonwook Jung, Sungwhan Seo, Sunghoon Kim, Moo Kyung Lee, Joo-Yong Park, James C. Kim, Young San Cha, Kwangwon Kim, Youngmin Jo, Hyunjin Kim, Youngdon Choi, Jindo Byun, Ji-hyun Park, Kiwon Kim, Tae-Hong Kwon, Youngsun Min, Chiweon Yoon, Youngcho Kim, Dong-Hun Kwak, Eungsuk Lee, Wook-ghee Hahn, Ki-sung Kim, Kyungmin Kim, Euisang Yoon, Won-Tae Kim, Inryoul Lee, Seung hyun Moon, Jeongdon Ihm, Dae Seok Byeon, Ki-Whan Song, Sangjoon Hwang, Kye Hyun Kyung An increase in the number of WL stacked layers results in degraded channel-hole variation [3], as shown in Fig. 13.4.4(a & b). Hence, to minimize this effect, an adaptive erase scheme is used to minimize erase Vth variation, as shown in Fig.

👥 作者与机构

apply a copy of the selected WL voltage to WLN+1, as shown in Fig. 13.4.3(b). This, technique improves the programming throughput by reducing the WL setup time