← 返回论文列表 📄 下载原文 PDF  ISSCC 2019 · 16.9
ISSCC 2019Session 16 · FREQUENCY SYNTHESIZERSClocking & PLLs0.18μm SiGe BiCMOS

GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文提出了一款基于0.18μm SiGe BiCMOS工艺的精确频率分数-N频率合成器,通过创新的杂散抑制技术实现了-80dBc的杂散性能,解决了传统分数-N PLL中由于数字ΔΣ调制器引入的分数杂散问题。

💡 主要创新点

核心指标
-80dBc杂散抑制 @ GHz频段
工艺节点
0.18μm SiGe BiCMOS
重要性
发表年份
ISSCC 2019

🏷 关键词

频率合成器分数-N杂散抑制SiGe BiCMOSΔΣ调制器

📄 原文摘要

Stefano Tulisi4, Sanganagouda Patil4, Ciarán Curtin4, Stephen Brookes4, Brian Shelly4, Patrick Griffin4, Michael Keaveney4 University College Dublin, Dublin, Ireland Microelectronic Circuits Centre Ireland, Dublin, Ireland 3 Microelectronic Circuits Centre Ireland, Cork, Ireland 4 Analog Devices, Limerick, Ireland 1 2 The instantaneous divide value of the multimodulus divider in the feedback path of a fractional-N PLL is determined by a divider controller, which is usually implemented as a digital delta-sigma modulator (DΔΣM). A disadvantage of the fractional-N PLL is the presence of fractional spurs, which result from interaction between the signal introduced by the DΔΣM and nonlinearities in the loop. When fractional spurs at frequencies close to integer boundaries lie inside the loop bandwidth, they cannot be attenuated by filtering. The Successive Requantizer (SR) is an alternative to the DΔΣM-based divider controller, which randomizes

👥 作者与机构

Michael Peter Kennedy1,2, Yann Donnelly1,3, James Breslin4,

分类:Clocking & PLLs · 年份:ISSCC 2019