⚡ 本页包含 AI 生成的分析内容，仅供参考
提出了一种用于下一代存储器接口的27Gb/s PAM-3单端收发器，采用单抽头判决反馈均衡器（DFE）来补偿信道间干扰（ISI），在保持单端信令的同时实现了高数据吞吐量。该设计解决了高速接口中功耗、面积和信号完整性之间的权衡问题。
high-data throughput while maintaining single-ended signaling and the supply voltage of I/O has been scaled down. Due to the increasing interface bandwidth the required area and power consumption has increased as well, resulting in higher I/O circuit design costs [3]. A high-loss channel causes ISI, which in turn limits the maximum data rate. Therefore, complex equalizers are needed for compensation, resulting in additional power dissipation and area overhead. As the data sampling rate increases, the deterministic and random noises degrade the data sampling margin and further limit the bandwidth. To lessen the negative impact of high channel loss and to reduce the forwarded clock frequency, multilevel signaling, such as PAM-4, can be used, as shown in Fig. 23.3.1 [2]. While
Hyunsu Park1, Junyoung Song2, Yeonho Lee1, Jincheol Sim1,
Jonghyuck Choi1, Chulwoo Kim1 Korea University, Seoul, Korea Incheon National University, Incheon, Korea 1 2 Bandwidths of memory interfaces have been increased tremendously to enable