A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and -70dBc Fractional Spurs

📋 论文概要

该论文提出了一种免校准的三环bang-bang PLL，用于解决数字PLL中TDC非线性和量化噪声问题。实现了131fsrms的极低抖动和-70dBc的分数杂散，满足WiFi 802.11ax等高性能标准的要求。

💡 主要创新点

• 提出三环bang-bang PLL架构，无需复杂校准即可实现高性能
• 通过独特的设计同时实现了超低抖动和低分数杂散
• 利用bang-bang PD的线性特性替代传统TDC，降低噪声

🏷 关键词

📄 原文摘要

standards, such as WiFi 802.11ax with a 1024-QAM mode, require RF clocks with extremely low integrated phase error and low spurs. Because of their good scalability, digital phase-locked loops (DPLLs) have been widely studied [1-3]. However, they face two problems: nonlinearity and quantization noise of time-to-digital converters (TDCs). High-performance DPLLs require complicated TDC structures and calibrations. By contrast, a bang-bang phase detector (PD), i.e. a one-bit TDC, can be linear and low noise [4]. However, in the fractional mode, the PD gain is lowered by the significant phase fluctuations from the fractional divider. The gain can be restored by calibration, but the nonlinearity of the calibration circuit creates

👥 作者与机构

Dihang Yang1, Asad Abidi1, Hooman Darabi2, Hao Xu1, David Murphy2,

Hao Wu2, Zhaowen Wang3 University of California, Los Angeles, CA Broadcom, Irvine, CA 3 Columbia University, New York, NY 1 2 To deliver a good EVM performance, modern communication