A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM output current of the I-SSCP is zero, which means the sampled input differential voltage (VSAM+-VSAM-) is around 0V. At the same time, (VP+-VP-) is also around 0V, and both VP+ and VP- are kept almost constant regardless of the output frequency.

📋 论文概要

提出一种0.65V低供电电压的子采样锁相环（SSPLL），通过采用高电平增强反相器（HBINV）提升SSPD的导通电压，解决了传统SSPD在低电压下性能退化的问题。实现了56.4fsrms的积分抖动和-256.4dB的品质因数（FoM）。

💡 主要创新点

• 采用高电平增强反相器（HBINV）将门控电压提升至约1V，显著降低了低电压下M1/M2的导通电阻，避免了采样信号的衰减。
• 基于子采样锁相环架构，在0.65V超低电源电压下实现了12至16GHz的宽频带范围和极低的抖动性能。

🏷 关键词

📄 原文摘要

To solve the issue of the conventional SSPD mentioned above, the LV SSPD (Fig. 30.8.3) is adopted. It adopts two high-level boosted inverters (HBINV) to enhance the turn-on voltage of the gate of M1 and M2 in the SSPD. The HBINV is modified based on the delay cell in [5]. The working principle of the HBINV is shown in Fig. 30.8.3. The post-layout simulation results of the HBINV (Fig. 30.8.3) verify that the output of the HBINV is boosted to around 1V with a 0.65V supply. As a result, the on-resistance of M1/M2 is significantly reduced even using a 0.65V supply. This prevents the attenuation of the sampled clock swing and lowers the in-band phase noise of the SSPLL induced by SSPD. M3 and M4 are inserted to compensate for the clock feedthrough from M1 and M2, respectively. Simulation results show that the sampled clock swing has a weak dependency on the SSPD input common-mode voltage VCM (from 0.1 to 0.5V). This helps to reduce the

👥 作者与机构

Zhao Zhang, Guang Zhu, C. Patrick Yue