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ISSCC 2019Session 19 · ADAPTIVE DIGITAL & CLOCKING TECHNIQUESDigital Circuits

A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput

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📋 论文概要

提出了一种可扩展的流水线时域动态时间规整(DTW)引擎,采用多比特时间触发器(MTFF)实现高速时间序列分类。解决了传统DTW加速器中单比特操作和固定序列长度的限制,实现了140Giga-C(每秒1400亿次比较)的处理能力。

💡 主要创新点

重要性
发表年份
ISSCC 2019

🏷 关键词

动态时间规整时域计算多比特时间触发器时间序列分类流水线架构

📄 原文摘要

Dynamic time warping (DTW), a variant of the dynamic programming algorithm, is widely used for time series classification [1]. Its strong capability for distance measurement for variable-speed temporal sequences makes DTW a popular method for time-series classification in broad applications, such as ECG diagnosis, motion detection, DNA sequencing, etc. [1]. Several efforts have proposed for accelerating the operation of DTW, including a recent demonstration of time-based design in DNA sequencing [2]. However, the demonstration was confined to single-bit operations, a fixed sequence length and low throughput due to nonpipelined operation and a large single-bit delay. To overcome such challenges, this work presents a general-purpose DTW engine for time-series classification using time-domain computing. Pipelined operation is enabled by a time flip-flop (TFF) leading to order-of-magnitude improvements in throughput and a scalable

👥 作者与机构

Zhengyu Chen, Jie Gu

Northwestern University, Evanston, IL

分类:Digital Circuits · 年份:ISSCC 2019