⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种28nm CMOS的12位5GS/s无源采样8倍交织混合模数转换器(ADC)，通过去除功耗大的前端缓冲器，实现了9.4 ENOB和158.6mW的低功耗，FoM_S达160.5dB，适用于5G通信系统。
Maarten Strackx2, Marcel J. M. Pelgrom1, Michiel Steyaert1, Marian Verhelst1, Filip Tavernier1 KU Leuven, Heverlee, Belgium Nokia Bell Labs, Antwerpen, Belgium 1 2 Emerging 5G communication systems require ADCs to directly digitize wide bandwidth (BW) signals with high spectral purity at low power consumption. Current state-of-the-art solutions include mainly time-interleaved (TI) pipelined [1-4] or pipelined-SAR [5] architectures, enhanced by digital calibration. To ensure a sufficiently high input BW, all these designs employ a static front-end buffer. This buffer often dissipates more power than the ADC itself, significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used [1-5]. This work aims to boost the input BW and dynamic performance, while minimizing the power of GHz-range high-resolution ADCs, with a 5GS/s passive-sampling,
Athanasios Ramkaj1, Juan Carlos Pena Ramos1, Yifan Lyu1,