A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS

📋 论文概要

该论文提出了一种计算调节的数字低压差稳压器（LDO），通过自主运行时增益跟踪技术，实现了2.79个时钟周期的平均建立时间，解决了传统数字LDO因采样反馈和PVT裕度导致的瞬态响应慢的问题。

💡 主要创新点

• 提出计算调节（Computationally Regulated）架构，通过数字计算优化控制环路，显著提升瞬态响应速度。
• 实现自主运行时增益跟踪（Autonomous Runtime Gain Track），动态调整环路增益以应对PVT变化，无需额外裕度。

🏷 关键词

📄 原文摘要

University of Washington, Seattle, WA Low-Dropout Regulators (LDOs) play an important role in enabling fine-grained supply-voltage domains for energy-efficient SoC design [1]. Digital LDOs are of particular interest due to integration and scalability advantages, but their transient response is slowed down by intrinsic limitations in sampled feedback systems. Design margins to ensure stability across worst-case PVT conditions further degrade transient response. Meanwhile, voltage domains continue to shrink in size, thus mandating a faster LDO response to compensate for reduced available decoupling capacitance (decap). Recently reported non-linear control and event-driven architectures offer fast recovery times [2] [3]. However, non-linear approaches face the challenge of ensuring stable mode transitions under random load current (IL) conditions. Event-driven LDOs trigger logic to control MOS devices based on threshold

👥 作者与机构

Xun Sun, Akshat Boora, Wenbing Zhang, Venkata Rajesh Pamula, Visvesh Sathe