A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS

📋 论文概要

本文提出一种56Gb/s PAM-4线缆接收器，采用增强模式利用CDR和遗传自适应算法，在模拟混合信号架构下实现低功耗。相比传统ADC-DSP或DFE接收器，该设计通过优化时钟恢复和均衡自适应，达到1.41pJ/b的能效。

💡 主要创新点

• 提出增强模式利用CDR技术，提高PAM-4信号时钟恢复的效率和鲁棒性。
• 引入遗传自适应算法用于均衡器系数优化，降低功耗并提升性能。
• 整体接收器采用模拟混合信号设计，避免大量锁存器，实现低功耗高速率传输。

🏷 关键词

📄 原文摘要

Ryan Bespalko1, Dustin Dunwell1, James Bailey1, Bo Wang1, Alireza Sharif-Bakhtiar1, Michael O'Farrell1, Kerry Tang1, Anthony Chan Carusone2, David Cassan1, Davide Tonietto3 Huawei Technologies, Toronto, Canada University of Toronto, Toronto, Canada 3 Huawei Technologies, Ottawa, Canada *Equally-Credited Authors (ECAs) 1 2 Analog mixed-signal (AMS) receivers for 50+Gb/s PAM-4 offer lower power than ADC-DSP receivers [1-3]. Those using DFEs [2-3] suffer from relatively high power consumption due to the large number of latches needed in PAM-4 speculative DFEs. Better power efficiency can be achieved using only a CTLE [1]. However, analog front-ends (AFEs) are sensitive to variations in process, supply voltage and temperature. To combat this while accommodating links with loss exceeding 20dB, an AFE with extensive programmability is combined with an efficient genetic adaptation algorithm to select a setting that minimizes BER thus

👥 作者与机构

Shayan Shahramian*1, Behzad Dehlaghi*1, Joshua Liang1,