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本文提出了一种基于VCO的5GS/s时间交织ADC，通过改进的高速低功耗环形振荡器和异步计数策略，实现了7.2 ENOB和30.5fJ/conv-step的能效，解决了传统VCO-ADC采样率和分辨率不足的问题。
Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs are able to benefit directly from improved digital performance [1]; however, the resolution and sampling rate of state-of-the-art VCO-based designs are insufficient for most applications. This paper presents a faster and more efficient VCO-based ADC architecture based on an improved high-speed, low-power ring oscillator and an asynchronous counting strategy. The architecture is 8× time-interleaved and combined with on-chip calibration. The design is implemented in 28nm CMOS and achieves 45.2dB SNDR (7.2 ENOB) near Nyquist at 5GS/s while consuming only 22.7mW, resulting in a Walden FOM of 30.5fJ/conv-step. The core area is only 0.023mm². These results demonstrate that VCO-based ADCs are a viable
Maarten Baert, Wim Dehaene
KU Leuven, Heverlee, Belgium