A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

📋 论文概要

本文提出了一种基于PAM-4的4通道复用和级联CDR电路的环形拓扑上行-下行接口，实现了25.6Gb/s的数据速率，解决了传统NAND接口在带宽和容量之间的权衡问题。

💡 主要创新点

• 采用PAM-4调制实现4通道复用，在有限带宽下提高数据传输效率。
• 设计级联CDR电路，在环形拓扑中同时支持上行和下行链路，降低负载电容影响。
• 采用环形拓扑结构替代传统多分支总线，减少NAND封装负载电容，支持更大容量。

🏷 关键词

📄 原文摘要

Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi Toshiba Memory, Kawasaki, Japan High-bandwidth (BW) and large-capacity storage systems with NAND Flash memory (hereinafter referred to as “NAND”) have been increasingly required for big data applications, such as the field of advanced biomedical science [1]. However, a conventional NAND interface (I/F), e.g. Toggle DDR, with multi-drop bus topology has a tradeoff between BW and capacity due to the large load capacitance of NAND packages (PKGs). Although increasing the number of parallelized lanes of Toggle DDR improves both BW and capacity, it costs a large number of pins/wires on a controller/PCB. In order to overcome these problems, a daisy-chained serial I/F has been proposed [2]. In the I/F, bridge chips mask large load capacitance of NAND PKGs seen from a controller’s transmitter (TX)

👥 作者与机构

Takashi Toi, Junji Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu,