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本文在7nm工艺下设计了一款2.1GHz的16Kb双端口SRAM，通过字线电阻电容（WL-RC）优化和虚拟读恢复电路，有效缓解了读干扰写（RDW）问题，提升了先进节点下双端口SRAM的性能与可靠性。
and wire routing resistance and capacitance; it degrades SRAM performance and results in SRAM design difficulties. Although dual-port (DP) SRAM is useful, because it can offer simultaneous read and write operations with two asynchronous clocks, circuit design is more complex than for a single-port (SP) SRAM when considering worst-case operation. In particular, WL resistance and capacitance (RC) degradation caused by process scaling and read-disturb-write (RDW) problem in a DP-SRAM bitcell are major challenges for DP-SRAM design in advanced technology nodes. In this paper, we report a 16Kb DP SRAM in a 7nm process technology with a 0.075um2 DP-SRAM bitcell. The DP bitcell improves wordline (WL)-RC and crosstalk between two WLs by process and layout co-optimization. The 16Kb DPSRAM includes a sequential power wakeup schem
Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin,
Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang TSMC, Hsinchu, Taiwan Continued transistor scaling increases random Vt variation,