A 7.5Gb/s/pin LPDDR5 SDRAM with WCK Clocking and

📋 论文概要

本文提出了一款采用WCK时钟和非目标ODT技术的7.5Gb/s/pin LPDDR5 SDRAM，实现了高速数据传输；同时结合DVFS、内部数据拷贝和深度睡眠模式，显著降低了功耗，解决了移动DRAM在高速与低功耗之间的权衡问题。

💡 主要创新点

• 引入WCK（写时钟）时钟方案，支持高速数据收发，提高信号完整性。
• 采用非目标ODT（片上终端）技术，优化高速下的阻抗匹配，降低反射和功耗。
• 集成动态电压频率缩放（DVFS）、内部数据拷贝和深度睡眠模式，实现灵活的低功耗管理。

🏷 关键词

📄 原文摘要

Data Copy, and Deep-Sleep Mode for Low Power Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyungjoon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, Seungseob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung-Hwan Choi, Tae-Young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang Samsung Electronics, Hwaseong, Korea High-speed and low-power techniques for the latest mobile DRAMs, such as LPDDR4/4X [1-3], have been developed to enable high-resolution displays, multiple cameras and 4G communication in mobile devices. However, DRAM with higher bandwidth and lower power consumption than LPDDR4X is indispensable to support 5G communication, on-device artificial intelligence and advanced driver assistance systems. In this paper, we present a 1st generation 10nm-class process

👥 作者与机构

Non-Target ODT for High Speed and with DVFS, Internal