A 0.01mm2 25μW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor coupled CT pipelined ADC is suitable for a wide range of applications where information does not reside at DC, such as audio, biological, and communication signals by setting the proper pass band frequencies.

📋 论文概要

该论文提出了一种连续时间流水线SAR ADC，采用两级结构：第一级为1位连续时间SAR，第二级为离散时间SAR，通过动态放大器替代静态闭环放大器以降低功耗。实现了0.01mm²面积、25μW功耗、2MS/s采样率下74dB SNDR，输入电容仅120fF，解决了高精度低功耗小面积ADC的设计难题。

💡 主要创新点

• 提出连续时间流水线SAR架构，第一级CT-SAR仅1位，使残差电压很小，从而允许使用低功耗动态放大器代替传统静态放大器。
• 采用自定时动态放大器，在固定放大时间后采样，结合两级流水线操作，实现高能效和高精度。
• 整体电路面积仅0.01mm²，输入电容仅120fF，适合低功耗高集成度应用。

🏷 关键词

📄 原文摘要

Shaolan Li1, Wenda Zhao1, Abhishek Mukherjee1, Nan Sun1 Figure 3.4.3 shows the overall schematic and timing diagram of the proposed ADC. At the rising edge of CLKsys, the 1st-stage CT SAR is triggered. After its operation finishes, the dynamic amplifier (DA) starts to amplify Vres. The DA is self-timed and its output is sampled after a fixed amount of amplification time. Then, the DT SAR is triggered to complete the 2nd-stage conversion. With the 1b 1st-stage CT-SAR, Vres is sufficiently small, allowing the use of a DA to replace the static closed-loop amplifier to reduce power consumption. For a conventional DA, its output common-mode voltage is usually not well-controlled and sensitive to PVT variations, which limits the available output signal swing. To address this issue, an inverter-based floating DA is proposed (Fig. 3.4.3). During the reset phase, CB is recharged to Vdd and ground. During the amplification phase, CB

👥 作者与机构

Linxiao Shen1, Yi Shen1,2, Xiyuan Tang1, Chen-Kai Hsu1, Wei Shi1,