⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一款基于ADC/DAC的收发器，支持1至56Gb/s连续速率PAM-4调制，在7nm FinFET工艺下实现低于250mW功耗和42.5dB插入损耗补偿。解决了高速有线通信中带宽增长与功耗控制的矛盾。
Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto Massolini, Giovanni Cesura, Ivan Bietti eSilicon Italy, Pavia, Italy The enormous availability of data on the internet and the increased computational power available in the cloud require a constant increase in the bandwidth needed to transport data across the network. In order to mitigate the cost of infrastructure, the industry has proposed standards for 56Gb/s PAM-4 interfaces that can support legacy channels in conjunction with forward error correction (FEC) techniques. The reduced signal to noise ratio (SNR) available with PAM-4 modulation vs. NRZ requires sophisticated signal processing, making DSP-based
Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani,