Wireline I/O — ISSCC 知识库

ISSCC 2019 Session 30 Wireline I/O

A 32Gb/s 2.9pJ/b Transceiver for Sequence-Coded PAM-4 Signalling with 4-to-6dB SNR Gain in 28nm FDSOI CMOS

Aurangozeb1, Carson Dick1, Maruf Mohammad2, Masum Hossain1

Intel, Santa Clara, CA 1 2 Multilevel signaling such as PAM-4 makes more efﬁcient use of the better part of the channel response by mapping multiple bits in the same time interval (i.e. UI). At the same time, to achieve

University of Alberta, Edmonton, Canada

ISSCC 2019 Session 30 Wireline I/O

A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

Takashi Toi, Junji Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu,

Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi Toshiba Memory, Kawasaki, Japan High-bandwidth (BW) and large-capacity storage systems with NAND Flash memory (h

ISSCC 2019 Session 30 Wireline I/O

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Gain Kim1,2,3, Lukas Kull2, Danny Luu2,4, Matthias Braendli2,

Cosimo Aprile1,2, Thomas Morf2, Marcel Kossel2, Alessandro Cevrero2, Ilter Ozkaya1,2, Andreas Burg1, Thomas Toiﬂ2, Yusuf Leblebici1 EPFL, Lausanne, Switzerland IBM Zurich Research Laboratory, Rueschlikon, Switzerland 3 *

Christian Menolﬁ2, Pier-Andrea Francese2, Hazar Yueksel5,

ISSCC 2019 Session 30 Wireline I/O

Single-Pair Automotive PHY Solutions from 10Mb/s to 10Gb/s and Beyond Gerrit W. den Besten

NXP Semiconductors, Eindhoven, The Netherlands, Car communication networks are rapidly evolving from a collection of sub

control busses to a high-performance data network for connecting sensors, processors, and actuators to enable autonomous driving [1]. A plurality of highbandwidth nodes like cameras, displays, radars, and wireless transc

ISSCC 2018 Session 6 Wireline I/O

A 32Gb/s 133mW PAM-4 Transceiver with DFE Based on Adaptive Clock Phase and Threshold Voltage in 65nm CMOS

Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang, Kai Sheng, Ai He

With the proliferation of the Internet of Things and mobile computing, network speed is accelerating to support data-rich services. This drives the explosion of bandwidth requirement on backplane interconnects while chan

Peking University, Beijing, China

ISSCC 2018 Session 6 Wireline I/O

A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR Transceiver in 28nm FDSOI CMOS

Emanuele Depaoli1, Enrico Monaco1, Giovanni Steffan1, Marco Mazzini1,

Hongyang Zhang2, Walter Audoglio1, Oscar Belotti1, Augusto Andrea Rossi1, Guido Albasini1, Massimo Pozzoni1, Simone Erba1, Andrea Mazzanti2 STMicroelectronics, Pavia, Italy University of Pavia, Pavia, Italy 1 2 PAM-4 mod

ISSCC 2018 Session 6 Wireline I/O

A 64Gb/s PAM-4 Transceiver Utilizing an Adaptive Threshold ADC in 16nm FinFET

Luke Wang1, Yingying Fu2, MarcAndre LaCroix3, Euhan Chong3, Anthony Chan Carusone1

for PAM-4 links above 50Gb/s [1,2], although fewer bits are sufficient and offer lower power for short reach (SR) channels. To further reduce the power consumption of ADC-based wireline transceivers, non-uniform quantiza

University of Toronto, Toronto, Canada Huawei, Markham, Canada 3 Huawe

ISSCC 2018 Session 6 Wireline I/O

A Fully Adaptive 19-to-56Gb/s PAM-4 Wireline Transceiver with a Configurable ADC in 16nm FinFET

Parag Upadhyaya1, Chi Fung Poon1, Siok Wei Lim2, Junho Cho1,

Arianne Roldan2, Wenfeng Zhang1, Jin Namkoong1, Toan Pham1, Bruce Xu1, Winson Lin1, Hongtao Zhang1, Nakul Narang2, Kee Hian Tan2, Geoff Zhang1, Yohan Frans1, Ken Chang1 Xilinx, San Jose, CA Xilinx, Singapore, Singapore 1

ISSCC 2018 Session 6 Wireline I/O

A 4-Lane 1.25-to-28.05Gb/s Multi-Standard 6pJ/b 40dB Transceiver in 14nm FinFET with Independent TX/RX Rate Support

Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus Mclaren,

Jennifer Pham, Kamran Farzan, Dominic Diclemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris Holdenried, Saman Sadr Rambus, Toronto, Canada The scaling of CMOS technology together with continued innovations i

ISSCC 2018 Session 6 Wireline I/O

A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

Christian Menolfi1, Matthias Braendli1, Pier Andrea Francese1,

Thomas Morf1, Alessandro Cevrero1, Marcel Kossel1, Lukas Kull1, Danny Luu1,2, Ilter Ozkaya1,3, Thomas Toifl1 IBM Zurich Research Laboratory, Rueschlikon, Switzerland 2 ETH Zurich, Zurich, Switzerland 3 EPFL, Lausanne, Sw

ISSCC 2018 Session 6 Wireline I/O

A 112Gb/s PAM-4 Transmitter with 3-Tap FFE in 10nm CMOS

Jihwan Kim, Ajay Balankutty, Rajeev Dokania, Amr Elshazly,

infrastructure has fueled the industry to develop ultra-high-speed/density wireline links compliant with electrical interface standards such as CEI-56G and 802.3bs400GbE. Recent publications have demonstrated CMOS transm

Hyung Seok Kim, Sandipan Kundu, Skyler Weaver, Kai Yu, Frank O'Mahony

ISSCC 2018 Session 25 Wireline I/O

A -242dB FOM and -75dBc-Reference-Spur Ring-DCO-Based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC

Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi

To improve efficiency in the use of silicon, there have been many efforts to develop ring-oscillator-based clock generators with low jitter. A PLL using a fast phaseerror correction (FPEC) technique [1] is one promising

Ulsan National Institute of Science and Technology, Ulsan, Korea

ISSCC 2018 Session 25 Wireline I/O

A Fractional-N Digital PLL with Background-DitherNoise-Cancellation Loop Achieving <-62.5dBc WorstCase Near-Carrier Fractional Spurs in 65nm CMOS

Cheng-Ru Ho, Mike Shuo-Wei Chen

Fractional-N digital phase-locked loops (DPLLs) are highly reconfigurable, scalable, and useful for synthesizing clocks with fine frequency resolution for modem RF, mixed-signal and digital VLSI systems. One critical des

University of Southern California, Los Angeles, CA

ISSCC 2018 Session 25 Wireline I/O

A 5GHz 370fsrms 6.5mW Clock Multiplier Using a Crystal-Oscillator Frequency Quadrupler in 65nm CMOS

Karim M. Megawer, Ahmed Elkholy, Daniel Coombs, Mostafa G. Ahmed,

(RO-based) clock multipliers is typically limited by oscillator noise. The most power-efficient method for improving the phase noise of such clock multipliers is by increasing the oscillator noise suppression bandwidth (

Ahmed Elmallah, Pavan Kumar Hanumolu University of Illinois, Urbana, I

ISSCC 2018 Session 25 Wireline I/O

A 4-to-16GHz Inverter-Based Injection-Locked Quadrature Clock Generator with Phase Interpolators for Multi-Standard I/Os in 7nm FinFET

attenuating the detected phase error signals. The outputs, Vdet_p and Vdet_n, are, averaged out by the V-to-I converter

suppress the supply noise, a voltage regulator is used to regulate the ILRO supply, Vreg_ILRO, which tracks Vctrl. Stanley Chen, Lei Zhou, Ian Zhuang, Jay Im, Didem Melek, Jinyung Namkoong, Mayank Raj, Jaewook Shin, Yoha

ISSCC 2018 Session 16 Wireline I/O

A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications

Yanghyo Kim1,2, Boyu Hu2, Yuan Du2, Adrian Tang1,2, Huan-Neng Chen3,

Taiwan 4 National Chiao Tung University, Hsinchu, Taiwan 1 2 Contactless chip-to-chip or board-to-board proximity (~1mm) communications have been realized by using either wireless transmission [1-3], or inductive/capacit

Chewnpu Jou3, Jason Cong2, Tatsuo Itoh2, Mau-Chung Frank Chang2,4 Jet

ISSCC 2018 Session 16 Wireline I/O

A 1.17pJ/b 25Gb/s/pin Ground-Referenced SingleEnded Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator

John M. Wilson1, Walker J. Turner1, John W. Poulton1, Brian Zimmer2,

Xi Chen2, Sudhir S. Kudva2, Sanquan Song2, Stephen G. Tell1, Nikola Nedovic2, Wenxu Zhao1a, Sunil R. Sudhakaran2, C. Thomas Gray1, William J. Dally2 Nvidia, Durham, NC; 2Nvidia, Santa Clara, CA 1 a now with Broadcom, Irv

ISSCC 2018 Session 16 Wireline I/O

A 126mW 56Gb/s NRZ Wireline Transceiver for Synchronous Short-Reach Applications in 16nm FinFET

Marc Erett1, Declan Carey1, James Hudner1, Ronan Casey1, Kevin Geary1,

Pedro Neto1, Mayank Raj2, Scott McLeod3, Hongtao Zhang2, Arianne Roldan2, Hongyuan Zhao4, Ping-Chuan Chiang4, Haibing Zhao4, KeeHian Tan4, Yohan Frans2, Ken Chang2 Xilinx, Cork, Ireland Xilinx, San Jose, CA 3 Acacia Comm

ISSCC 2018 Session 16 Wireline I/O

A 7.8Gb/s/pin 1.96pJ/b Compact Single-Ended TRX and CDR with Phase-Difference Modulation for Highly Reflective Memory Interfaces

Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, Jae-Yoon Sim,

strongly demanded by the memory industry. Although discontinuous reflective channels like multi-drop DRAM interfaces are less suitable for high data rates than continuous point-to-point channels, their great advantages i

Hong-June Park, Byungsub Kim Pohang University of Science and Technolo

ISSCC 2018 Session 16 Wireline I/O

A 20Gb/s Transceiver with Framed-Pulsewidth Modulation in 40nm CMOS

Sejun Jeon1, Woohyun Kwon1, Taehun Yoon2, Jong-Hyeok Yoon1,

interference (ISI), which necessitates the enhancement of spectral efficiency. Recently, various modulation schemes including pulse amplitude modulation (PAM) [1], pulsewidth modulation (PWM) [2], permutation modulation

Kyeongha Kwon1, Jaehyeok Yang1, Hyeon-Min Bae1 KAIST, Daeoen, Korea 2

ISSCC 2018 Session 16 Wireline I/O

A 56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS

Ilter Ozkaya1,2, Alessandro Cevrero1, Pier Andrea Francese1,

Christian Menolfi1, Matthias Braendli1, Thomas Morf1, Dan Kuchta3, Lukas Kull1, Marcel Kossel1, Danny Luu1, Mounir Meghelli3, Yusuf Leblebici2, Thomas Toifl1 IBM Research, Ruschlikon, Switzerland EPFL, Lausanne, Switzerl

ISSCC 2018 Session 16 Wireline I/O

A 28Gb/s Transceiver with Chirp-Managed EDC for DML Systems

Kyeongha Kwon, Jonghyeok Yoon, Hanho Choi, Younho Jeon,

medium-reach optical links owing to their simplicity and cost effectiveness. However, the chirp phenomenon under direct modulation limits the reach (2-10km) in a standard single-mode fiber (SMF). Although diverse optical

Jaehyeok Yang, Bongjin Kim, Soonwon Kwon, Minsik Kim, Sejun Jeon, Hyos

ISSCC 2017 Session 6 Wireline I/O

A 28Gb/s Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance

Joshua Liang1, Ali Sheikholeslami1, Hirotaka Tamura2, Yuuki Ogata2, Hisakatsu Yamaguchi2

(CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes th

University of Toronto, Toronto, Canada Fujitsu Laboratories, Kawasaki,

ISSCC 2017 Session 6 Wireline I/O

A 22.5-to-32Gb/s 3.2pJ/b Referenceless Baud-Rate Digital CDR with DFE and CTLE in 28nm CMOS

Wahid Rahman1, Danny Yoo1, Joshua Liang1, Ali Sheikholeslami1,

circuits (CDRs) are becoming more prevalent in high-speed receiver designs as they offer lower power consumption by sampling the received data only once per UI [1,2]. This reduces the number of front-end comparators and

Hirotaka Tamura2, Takayuki Shibasaki2, Hisakatsu Yamaguchi2 University

ISSCC 2017 Session 6 Wireline I/O

A 1.8pJ/b 56Gb/s PAM-4 Transmitter with Fractionally Spaced FFE in 14nm CMOS

Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli

As data rates in electrical links rise to 56Gb/s, standards are gravitating towards PAM-4 modulation to achieve higher spectral efficiency. Such approaches are not without drawbacks, as PAM-4 signaling results in reduced

IBM T. J. Watson Research Center, Yorktown Heights, NY

ISSCC 2017 Session 6 Wireline I/O

A 64Gb/s PAM-4 Transmitter with 4-Tap FFE and 2.26pJ/b Energy Efficiency in 28nm CMOS FDSOI

Giovanni Steffan1, Emanuele Depaoli1, Enrico Monaco1, Nicolo Sabatino1,

Walter Audoglio1, Augusto Andrea Rossi1, Simone Erba1, Matteo Bassi2, Andrea Mazzanti2 STMicroelectronics, Pavia, Italy University of Pavia, Pavia, Italy 1 2 Electrical link migration requires serial interfaces to operat

ISSCC 2017 Session 6 Wireline I/O

A 40-to-56Gb/s PAM-4 Receiver with 10-Tap Direct Decision-Feedback Equalization in 16nm FinFET

Jay Im1, Dave Freitas1, Arianne Roldan2, Ronan Casey3, Stanley Chen1,

Adam Chou1, Tim Cronin1, Kevin Geary3, Scott McLeod1, Lei Zhou1, Ian Zhuang1, Jaeduk Han4, Sen Lin4, Parag Upadhyaya1, Geoff Zhang1, Yohan Frans1, Ken Chang1 Xilinx, San Jose, CA Xilinx, Singapore, Singapore 3 Xilinx, Co

ISSCC 2017 Session 6 Wireline I/O

A 60Gb/s 288mW NRZ Transceiver with Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65nm CMOS Technology

Jaeduk Han1, Yue Lu2, Nicholas Sutardja1, Elad Alon1

Qualcomm Atheros, San Jose, CA 1 2 The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decr

University of California, Berkeley, CA

ISSCC 2017 Session 6 Wireline I/O

A 56Gb/s PAM-4/NRZ Transceiver in 40nm CMOS

Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee

Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/dese

National Taiwan University, Taipei, Taiwan

ISSCC 2017 Session 29 Wireline I/O

A 2.5GHz Injection-Locked ADPLL with 197fsrms Integrated Jitter and -65dBc Reference Spur Using Time-Division Dual Calibration

Sungwoo Kim1, Han-Gon Ko1, Sung-Yong Cho1, Jinhyung Lee1,

7.3 shows the implemented schematic of the TDDC. The ILO is based on a pseudo-differential 4-stage ring oscillator, whose frequency is controlled by the 10b FCW. The frequency resolution is 100kHz/LSB. The FEPMD controls

Soyeong Shin1, Min-Seong Choo1, Hankyu Chi2, Deog-Kyoon Jeong1 Seoul N

ISSCC 2017 Session 29 Wireline I/O

A 3-to-10Gb/s 5.75pJ/b Transceiver with Flexible Clocking in 65nm CMOS

Romesh Kumar Nandwana1, Saurabh Saxena2, Ahmed Elkholy1,

This 2-step truncation and cancellation method provides higher order modulation while avoiding -1 to 1 and 1 to -1 jumps, which limits the needed DCDL range to 1 cycle of CKHF, independent of output frequency/data rate.

Mrunmay Talegaonkar1, Junheng Zhu1, Woo-Seok Choi1, Ahmed Elmallah1, P

ISSCC 2017 Session 29 Wireline I/O

12Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling with 100% Data Payload and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces

Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun,

29.5.1 is generally adopted in an intra-panel interface due to the poor signal integrity of the multi-drop topology, data and clock channel skews and EMI emission from the forwarded clock signal channels. Clock recovery

Junyoung Song, Sewook Hwang, Chulwoo Kim Korea University, Seoul, Kore

ISSCC 2017 Session 29 Wireline I/O

A 16Gb/s 3.6pJ/b Wireline Transceiver with Phase Domain Equalization Scheme: Integrated Pulse Width Modulation (iPWM) in 65nm CMOS

Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand

Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FF

Oregon State University, Corvallis, OR

ISSCC 2017 Session 29 Wireline I/O

A 40Gb/s PAM-4 Transmitter Based on a RingResonator Optical DAC in 45nm SOI CMOS

Sajjad Moazeni1, Sen Lin1, Mark T. Wade2, Luca Alloatti3, Rajeev J. Ram4,

Milos A. Popovic5, Vladimir Stojanovic1 University of California, Berkeley, CA Ayar Labs, San Francisco, CA 3 ETH Zurich, Zurich, Switzerland 4 Massachusetts Institute of Technology, Cambridge, MA 5 Boston University, Bo

ISSCC 2017 Session 29 Wireline I/O

A Transmitter and Receiver for 100Gb/s Coherent Networks with Integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS

Jun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Catli,

Mehdi Khanpour, Kangmin Hu, Tamer Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz Broadcom, Irvine, CA At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated wit

ISSCC 2017 Session 29 Wireline I/O

A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET

Alessandro Cevrero1, Ilter Ozkaya1,3, Pier Andrea Francese1,

Christian Menolfi1, Thomas Morf1, Matthias Brandli1, Dan Kuchta2, Lukas Kull1, Jon Proesel2, Marcel Kossel1, Danny Luu1, Benjamin Lee2, Fuad Doany2, Mounir Meghelli2, Yusuf Leblebici3, Thomas Toifl1 IBM Research, Rueschl